ddr
所属分类:VHDL/FPGA/Verilog
开发工具:Others
文件大小:2KB
下载次数:88
上传日期:2006-04-21 09:00:58
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changking23
说明: 本人正在学习vhdl语言,买了套开发板,这些是配套光盘里的内容,非常难得,网上找不到的
(I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !)
文件列表:
ddr\verilog\DDR_3state.v (934, 2001-03-23)
ddr\verilog\DDR_Input.v (732, 2001-03-23)
ddr\verilog\DDR_Output.v (558, 2001-03-23)
ddr\verilog (0, 2006-04-20)
ddr (0, 2006-04-20)
README file: Virtex-II Platform FPGA Handbook
=============================================
Date: March, 2001
Verilog code examples are provided to illustrate the Chapter 2 - Design Considerations - of
the Virtex-II Platform FPFA Handbook.
- Verilog Templates:
Verilog templates are available as examples to instantiate primitives.
- Verilog Submodules:
Verilog submodules are low level Verilog code instantiating some primitives.
These submodules can be instantiated in a design and must be synthesized with the design.
The templates and submodules can be found in the following directories corresponding to
each section of the Chapter 2: Design Considerations (Virtex-II Platform FPGA HandBook)
Directory:
------------
- ddr: "Using DDR I/O"
Templates (primitive):
DDR_Input
DDR_Output
DDR_3state
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