non_continues_ifft
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：3244KB
下载次数：5
上传日期：2012-01-04 20:49:18
上 传 者：
解析几何
说明： 非流水线数据输入方式的FFT调核实现，功仿正确，由于采用基2的方式，输出需花很长的时间，因此，前面需要加载FIFO存取中间来的数据，保证FFT处理的时间。因此，对输入数据流的时钟频率不能太高！
(Non-pipelined FFT of input data transfer nuclear achieved successful imitation is correct, the way thanks to the base 2, the output need to spend a long time, therefore, need to load the previous FIFO access to the data center to ensure the FFT processing time. Therefore, the clock frequency of the input data stream can not be too high!)
文件列表:
non_continues_ifft\.lso (6, 2012-01-04)
non_continues_ifft\coregen.cgp (534, 2012-01-04)
non_continues_ifft\coregen.log (0, 2012-01-04)
non_continues_ifft\coregen.rsp (303, 2012-01-04)
non_continues_ifft\core_resources.txt (20, 2012-01-04)
non_continues_ifft\data_gen.cmd_log (340, 2012-01-04)
non_continues_ifft\data_gen.lso (6, 2012-01-04)
non_continues_ifft\data_gen.ngc (13108, 2012-01-04)
non_continues_ifft\data_gen.ngr (6669, 2012-01-04)
non_continues_ifft\data_gen.prj (30, 2012-01-04)
non_continues_ifft\data_gen.stx (887, 2012-01-04)
non_continues_ifft\data_gen.syr (14665, 2012-01-04)
non_continues_ifft\data_gen.xst (1269, 2012-01-04)
non_continues_ifft\data_gen_module_tb.udo (121, 2012-01-04)
non_continues_ifft\data_gen_module_tb_wave.fdo (138, 2012-01-04)
non_continues_ifft\data_gen_module_xst.xrpt (4277, 2012-01-04)
non_continues_ifft\data_gen_tb.fdo (358, 2012-01-04)
non_continues_ifft\data_gen_tb.udo (114, 2012-01-04)
non_continues_ifft\data_gen_tb.vhd (2221, 2012-01-04)
non_continues_ifft\data_gen_tb_wave.fdo (131, 2012-01-04)
non_continues_ifft\data_gen_vhdl.prj (57, 2012-01-04)
non_continues_ifft\data_gen_xst.xrpt (4263, 2012-01-04)
non_continues_ifft\data_valid_gen.ngc (3438, 2012-01-04)
non_continues_ifft\data_valid_gen.ngr (2974, 2012-01-04)
non_continues_ifft\data_valid_gen.vhd (2475, 2012-01-04)
non_continues_ifft\data_valid_gen_tb.udo (120, 2012-01-04)
non_continues_ifft\data_valid_gen_tb.vhd (2174, 2012-01-04)
non_continues_ifft\data_valid_gen_tb_wave.fdo (137, 2012-01-04)
non_continues_ifft\data_valid_gen_xst.xrpt (4273, 2012-01-04)
non_continues_ifft\fft_16.asy (1647, 2012-01-04)
non_continues_ifft\fft_16.ngc (537007, 2012-01-04)
non_continues_ifft\fft_16.sym (2805, 2012-01-04)
non_continues_ifft\fft_16.v (696996, 2012-01-04)
non_continues_ifft\fft_16.veo (3314, 2012-01-04)
non_continues_ifft\fft_16.vhd (841198, 2012-01-04)
non_continues_ifft\fft_16.vho (4116, 2012-01-04)
non_continues_ifft\fft_16.xco (1896, 2012-01-04)
non_continues_ifft\fft_16_flist.txt (223, 2012-01-04)
non_continues_ifft\fft_16_xfft_v5_0_xst_1.ngc_xst.xrpt (6024, 2012-01-04)
... ...
The following files were generated for 'fft_16' in directory
E:\test\non_continues_ifft:
core_resources.txt:
Please see the core data sheet.
fft_16.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
fft_16.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
fft_16.sym:
Please see the core data sheet.
fft_16.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
fft_16.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
fft_16.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
fft_16.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
fft_16.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
fft_16_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
fft_16_readme.txt:
Text file indicating the files generated and how they are used.
fft_16_xfft_v5_0_xst_1.ngc_xst.xrpt:
Please see the core data sheet.
fft_16_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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