1553B_enc_dec
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：177KB
下载次数：38
上传日期：2012-01-08 16:30:58
上 传 者：
dragon_w_123
说明： 155B航空总线中曼彻斯特编码和译码模块，亲测可以使用，而且很好用，但是对锁相环的描述不是很仔细
(155B Air bus Manchester encoding and decoding modules, pro-test can be used, and it just works)
文件列表:
1553B_enc_dec\docs\rd1021.pdf (29250, 2004-07-23)
1553B_enc_dec\par\EC\decoder_1553.prf (1829, 2004-06-28)
1553B_enc_dec\par\EC\decoder_1553.syn (293, 2004-06-28)
1553B_enc_dec\par\EC\encoder_1553.prf (1846, 2004-06-28)
1553B_enc_dec\par\EC\encoder_1553.syn (259, 2004-06-28)
1553B_enc_dec\simulation\EC\scripts\1553B_enc_dec.fsdb (13962, 2011-09-14)
1553B_enc_dec\simulation\EC\scripts\result.log (2375, 2011-09-14)
1553B_enc_dec\simulation\EC\scripts\runsim_1553.do (326, 2004-07-02)
1553B_enc_dec\simulation\EC\scripts\sim.do (381, 2011-09-21)
1553B_enc_dec\simulation\EC\scripts\vsim.wlf (65536, 2011-09-14)
1553B_enc_dec\simulation\EC\scripts\work\decoder_1553\verilog.asm (17345, 2011-09-14)
1553B_enc_dec\simulation\EC\scripts\work\decoder_1553\_primary.dat (2448, 2011-09-14)
1553B_enc_dec\simulation\EC\scripts\work\decoder_1553\_primary.vhd (460, 2011-09-14)
1553B_enc_dec\simulation\EC\scripts\work\encoder_1553\verilog.asm (19890, 2011-09-14)
1553B_enc_dec\simulation\EC\scripts\work\encoder_1553\_primary.dat (2166, 2011-09-14)
1553B_enc_dec\simulation\EC\scripts\work\encoder_1553\_primary.vhd (460, 2011-09-14)
1553B_enc_dec\simulation\EC\scripts\work\test_1553\verilog.asm (13218, 2011-09-14)
1553B_enc_dec\simulation\EC\scripts\work\test_1553\_primary.dat (2439, 2011-09-14)
1553B_enc_dec\simulation\EC\scripts\work\test_1553\_primary.vhd (78, 2011-09-14)
1553B_enc_dec\simulation\EC\scripts\work\_info (636, 2011-09-14)
1553B_enc_dec\source\decoder_1553.v (6837, 2011-09-14)
1553B_enc_dec\source\encoder_1553.v (6189, 2011-09-14)
1553B_enc_dec\synthesis\EC\synplify\decoder_1553.prd (289, 2011-09-14)
1553B_enc_dec\synthesis\EC\synplify\decoder_1553.prj (1572, 2011-09-14)
1553B_enc_dec\synthesis\EC\synplify\decoder_1553.sdc (1215, 2011-09-14)
1553B_enc_dec\synthesis\EC\synplify\encoder_1553.prd (289, 2011-09-14)
1553B_enc_dec\synthesis\EC\synplify\encoder_1553.prj (1427, 2011-09-14)
1553B_enc_dec\synthesis\EC\synplify\encoder_1553.sdc (1214, 2011-09-14)
1553B_enc_dec\synthesis\EC\synplify\rev_1\backup\decoder_1553.srr (17345, 2011-09-14)
1553B_enc_dec\synthesis\EC\synplify\rev_1\decoder_1553.edf (88544, 2011-12-04)
1553B_enc_dec\synthesis\EC\synplify\rev_1\decoder_1553.fse (0, 2011-12-04)
1553B_enc_dec\synthesis\EC\synplify\rev_1\decoder_1553.map (28, 2011-12-04)
1553B_enc_dec\synthesis\EC\synplify\rev_1\decoder_1553.ncf (0, 2011-12-04)
1553B_enc_dec\synthesis\EC\synplify\rev_1\decoder_1553.sap (2353, 2011-12-04)
1553B_enc_dec\synthesis\EC\synplify\rev_1\decoder_1553.srd (10952, 2011-12-04)
1553B_enc_dec\synthesis\EC\synplify\rev_1\decoder_1553.srm (82685, 2011-12-04)
1553B_enc_dec\synthesis\EC\synplify\rev_1\decoder_1553.srr (17406, 2011-12-04)
1553B_enc_dec\synthesis\EC\synplify\rev_1\decoder_1553.srs (6621, 2011-09-14)
1553B_enc_dec\synthesis\EC\synplify\rev_1\decoder_1553.szr (13220, 2011-12-04)
... ...
1553 decoder-encoder Reference Design
===============================================================================
File List
1. /1553_enc_dec/docs/1553_enc_dec.doc --> Design document
/1553_enc_dec/docs/readme.txt --> Read me file
2. /1553_enc_dec/source/decoder_1553.v --> Decoder source verilog file
/1553_enc_dec/source/encoder_1553.v --> Encoder source verilog file
3. /1553_enc_dec/par/EC/decoder_1553.prf --> Decoder Constraint file for place and route
/1553_enc_dec/par/EC/encoder_1553.prf --> Encoder Constraint file for place and route
/1553_enc_dec/par/EC/decoder_1553.syn --> Decoder Project file for place and route
/1553_enc_dec/par/EC/encoder_1553.syn --> Encoder Project file for place and route
4. /1553_enc_dec/simulation/EC/scripts/runsim_1553.do --> Scripts for RTL simulation
5. /1553_enc_dec/synthesis/EC/synplify/decoder_1553.prj --> Decoder Project file for synthesis using synplify
/1553_enc_dec/synthesis/EC/synplify/encoder_1553.prj --> Encoder Project file for synthesis using synplify
/1553_enc_dec/synthesis/EC/synplify/decoder_1553.sdc --> Decoder Constraint file for synthesis using synplify
/1553_enc_dec/synthesis/EC/synplify/encoder_1553.sdc --> Encoder Constraint file for synthesis using synplify
6. /1553_enc_dec/testbench/test_1553.v --> Testbench for simulation
Synthesis
1. Launch synplify
2. Correct the source file pathname in the encoder_1553.prj
3. Open project /1553_enc_dec/synthesis/EC/synplify/encoder_1553.prj
4. Click [Run]
Place and Route
1. Launch ispLEVER
2. Open project "/1553_enc_dec/par/EC/encoder_1553.syn"
3. Click "Place and Route Trace Report" on right pannel
Simulation
1. Launch modelsim oem edition
2. Click [File] --> [Change Directory...] and select "/1553_enc_dec/simulation/EC/scripts"
3. Click [Tools] --> [Excute Macro]
simulation, select "/1553_enc_dec/simulation/EC/scripts/runsim_1553.do"
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