soc
所属分类：VHDL/FPGA/Verilog
开发工具：Asm
文件大小：3596KB
下载次数：11
上传日期：2012-01-19 09:29:25
上 传 者：
anzheng2011
说明： 精简的单周期CPU设计代码，适合SOC设计初学者,基本模块包括LED，switch bar，seven segment
(Streamlined single-cycle CPU design code for SOC design for beginners, basic modules include
)
文件列表:
soc (0, 2012-01-19)
soc\asm (0, 2012-01-19)
soc\asm\chang.coe (278, 2012-01-11)
soc\asm\chang1.asm (649, 2012-01-11)
soc\asm\chang1.bin (84, 2012-01-11)
soc\asm\mylab.asm (674, 2012-01-11)
soc\asm\mylab.bin (92, 2012-01-11)
soc\asm\mylab.coe (298, 2012-01-11)
soc\asm\run.asm (1214, 2012-01-11)
soc\asm\run.bin (208, 2012-01-11)
soc\asm\run.coe (594, 2012-01-11)
soc\asm\top1.bit (464302, 2012-01-11)
soc\soc_work (0, 2012-01-19)
soc\soc_work\coregen_xil_26360_93.cgc (2075, 2011-12-06)
soc\soc_work\coregen_xil_26360_93.cgp (518, 2011-12-06)
soc\soc_work\div_clock.v (940, 2012-01-04)
soc\soc_work\inst.coe (114, 2011-12-06)
soc\soc_work\inst_rom.mif (170, 2011-12-06)
soc\soc_work\ipcore_dir (0, 2012-01-19)
soc\soc_work\ipcore_dir\.lso (19, 2012-01-11)
soc\soc_work\ipcore_dir\coregen.cgc (26188, 2012-01-11)
soc\soc_work\ipcore_dir\coregen.cgp (246, 2011-12-06)
soc\soc_work\ipcore_dir\coregen.log (1639, 2012-01-11)
soc\soc_work\ipcore_dir\coregen.rsp (130, 2012-01-11)
soc\soc_work\ipcore_dir\data_ram.asy (524, 2011-12-06)
soc\soc_work\ipcore_dir\data_ram.gise (2811, 2012-01-11)
soc\soc_work\ipcore_dir\data_ram.ncf (0, 2012-01-11)
soc\soc_work\ipcore_dir\data_ram.ngc (74771, 2011-12-06)
soc\soc_work\ipcore_dir\data_ram.sym (1547, 2011-12-06)
soc\soc_work\ipcore_dir\data_ram.v (6414, 2011-12-06)
soc\soc_work\ipcore_dir\data_ram.veo (4625, 2011-12-06)
soc\soc_work\ipcore_dir\data_ram.vhd (6843, 2011-12-06)
soc\soc_work\ipcore_dir\data_ram.vho (5097, 2011-12-06)
soc\soc_work\ipcore_dir\data_ram.xco (2838, 2011-12-06)
soc\soc_work\ipcore_dir\data_ram.xise (5032, 2011-12-06)
soc\soc_work\ipcore_dir\data_ram_flist.txt (289, 2011-12-06)
soc\soc_work\ipcore_dir\data_ram_xmdf.tcl (3362, 2011-12-06)
soc\soc_work\ipcore_dir\dist_mem_gen_ds322.pdf (717971, 2012-01-11)
... ...
The following files were generated for 'inst_rom' in directory
D:\Xilinx\soc_work\soc_work\ipcore_dir\
dist_mem_gen_ds322.pdf:
Please see the core data sheet.
dist_mem_gen_readme.txt:
Text file indicating the files generated and how they are used.
inst_rom.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
inst_rom.gise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
inst_rom.mif:
Memory Initialization File which is automatically generated by the
CORE Generator System for some modules when a simulation flow is
specified. A MIF data file is used to support HDL functional
simulation of modules which use arrays of values.
inst_rom.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
inst_rom.sym:
Please see the core data sheet.
inst_rom.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
inst_rom.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
inst_rom.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
inst_rom.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
inst_rom.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
inst_rom.xise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
inst_rom_readme.txt:
Text file indicating the files generated and how they are used.
inst_rom_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
inst_rom_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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