ARMCORE
所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:671KB
下载次数:15
上传日期:2012-02-06 10:53:03
上 传 者:
niuer19861985
说明: arm7的内核,包括arm ip代码和仿真结果
(ARM7 core,include arm code and simulation result)
文件列表:
ARMCORE\26_1000\Adder.v (2313, 2001-07-12)
ARMCORE\26_1000\ALUComb.v (6940, 2001-07-05)
ARMCORE\26_1000\ALUShell.v (34356, 2001-09-05)
ARMCORE\26_1000\bak\Arbitrator.v (320, 2001-04-09)
ARMCORE\26_1000\bak\BusTransfer.v (618, 2000-04-26)
ARMCORE\26_1000\bak\CacheMemory.v (2447, 2000-05-03)
ARMCORE\26_1000\bak\CAM.v (1094, 2000-05-03)
ARMCORE\26_1000\bak\datac2.v (1291, 2000-05-03)
ARMCORE\26_1000\bak\DataCacheController.v (22340, 2001-07-23)
ARMCORE\26_1000\bak\DataCacheMemory.v (2065, 2000-05-03)
ARMCORE\26_1000\bak\Def_ComponentEntry.v (83, 2001-04-08)
ARMCORE\26_1000\bak\InstructionCacheController.v (15712, 2001-05-14)
ARMCORE\26_1000\bak\InstructionPreFetch.v (9248, 2001-07-23)
ARMCORE\26_1000\bak\MemoryController.v (5366, 2001-06-08)
ARMCORE\26_1000\bak\MemoryMux.v (406, 2000-05-06)
ARMCORE\26_1000\bak\nnARM.v (22226, 2001-07-04)
ARMCORE\26_1000\bak\nnARM11.v (5223, 2001-07-18)
ARMCORE\26_1000\bak\scr.cmd (1482, 2001-05-22)
ARMCORE\26_1000\bak\System.v (2906, 2001-03-24)
ARMCORE\26_1000\bak\tb_Adder.v (814, 2001-04-18)
ARMCORE\26_1000\bak\tb_BarrelShift.v (1038, 2001-04-15)
ARMCORE\26_1000\bak\tb_complementary.v (423, 2001-04-16)
ARMCORE\26_1000\bak\tb_Decoder_ARM.v (90, 2000-04-25)
ARMCORE\26_1000\bak\tb_IF.v (2029, 2001-04-06)
ARMCORE\26_1000\bak\tb_InstructionPreFetch.v (2297, 2001-04-06)
ARMCORE\26_1000\bak\tb_RegisterFile.v (1089, 2001-04-07)
ARMCORE\26_1000\bak\tb_system_fft.v (1607, 2001-06-06)
ARMCORE\26_1000\bak\tb_tomasulo.v (5730, 2001-04-10)
ARMCORE\26_1000\bak\TestInstruction.v (206, 2001-04-10)
ARMCORE\26_1000\bak (0, 2006-02-28)
ARMCORE\26_1000\BarrelShift.v (6109, 2001-07-04)
ARMCORE\26_1000\CanGoGen.v (509, 2000-05-01)
ARMCORE\26_1000\complementary.v (848, 2001-04-16)
ARMCORE\26_1000\Decoder_ARM.v (89045, 2001-09-05)
ARMCORE\26_1000\Def_ALUType.v (1927, 2001-05-23)
ARMCORE\26_1000\Def_ARMALU.v (488, 2001-04-07)
ARMCORE\26_1000\Def_BarrelShift.v (371, 2001-07-04)
ARMCORE\26_1000\Def_ConditionField.v (1777, 2001-03-16)
ARMCORE\26_1000\Def_DataCacheController.v (682, 2001-05-10)
ARMCORE\26_1000\Def_Decoder.v (2242, 2001-08-28)
... ...
-------------------- synthsis files -----------------------------------------
Adder.v contain WordAdder module that add two 32bit word together
ALUComb.v The combinatinal logic module ALUComb perform varies ALU operation auch as Add , Or , Not. this module is mounted on ALUShell with is part of nnARM pipeline
ALUShell.v ALUShell module is the EXE stage of pipeline
BarrelShifter.v BarrelShifter is instance in ALUComb to perform varies type of shift operation
CanGoGen.v CanGoGen module perform pipeline interlock signal generation
complementory.v generate complementory value of B and put it to adder when perform A-B operation in ALUComb module
DataCacheContaoller.v this is the behavior level description of data cache.
Decoder_ARM Decoder_ARM module is the decode stage of pipeline
IF.v instruction fetch stage of pipeline
InstructionCacheController.v behavior decription of instruction cache
InstructionPrefetch.v Instruction prefetch stage of pipeline
mem.v MEM stage of pipeline
MemoryController.v the behavior description of memory
mul.v a function to perform 32 bit multiple
nnARMCore.v top level synthesis module of nnARM, it contain all nnARM component
psr.v CPSR and SPSR register
RegisterFile.v 3 read and 2 write register file
Thumb_2_nnARM.v translate Thumb code to nnARM instruction
ThumbDecoderWarper.v pack Thumb_2_nnARM and the switchs to form a new module
InterruptPriority.v decide if varies interrupt can generate
PSR_Fresh.v use to generate the most fresh version of CPSR from within pipeline, because some pipeline stage may change CPSR value
---------------------- simulation files --------------------------------------------------------------
nnARM.prog this file is a record about the development of nnARM, it is in Chinese plain text
nnARM1.v interconnect nnARMCore module with cache and memory, this is only use to simulate nnARM, no use in synthesis
tb_system.v top level simulate module
timescalar.v simulation time unit
-----------------------file define something use both in synthesis and simulate---------------------
Def_XXXX.v
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