说明：  verilog HDL写的时钟通用计数分频程序，设置系统时钟，并根据目标时钟，设置分频系数即可得到目标时钟。已实际测试可用。
(verilog HDL write clock common procedures for the count and divide, set the system clock, and the root According to the target clock, set the frequency division factor can get the target clock. Have been actual tested )