5.1-PCF8563
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：2369KB
下载次数：10
上传日期：2012-03-26 21:45:42
上 传 者：
zhaowanyun
说明： 基于pcf8563的数字钟设计，erilog语言编写，以调试
(digital clock based on erilog langrage)
文件列表:
5.1 PCF8563 (0, 2012-03-03)
5.1 PCF8563\Verilog (0, 2012-03-05)
5.1 PCF8563\Verilog\db (0, 2012-03-05)
5.1 PCF8563\Verilog\db\altsyncram_0hq1.tdf (67399, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_1hq1.tdf (68565, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_27p3.tdf (3532, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_2hq1.tdf (35917, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_31t3.tdf (274404, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_3hq1.tdf (37083, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_4hq1.tdf (264941, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_5hq1.tdf (37083, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_5ss3.tdf (3611, 2010-03-02)
5.1 PCF8563\Verilog\db\altsyncram_67p3.tdf (3546, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_6hq1.tdf (47577, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_7hq1.tdf (49909, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_7ss3.tdf (3621, 2010-03-02)
5.1 PCF8563\Verilog\db\altsyncram_87p3.tdf (3546, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_9ps3.tdf (3578, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_9ss3.tdf (3585, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_bps3.tdf (3579, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_bss3.tdf (3592, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_c7p3.tdf (3548, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_d7p3.tdf (3543, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_dss3.tdf (3593, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_e7p3.tdf (3556, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_egq1.tdf (16077, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_f1t3.tdf (543220, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_fss3.tdf (3625, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_g1t3.tdf (274138, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_gss3.tdf (3622, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_hss3.tdf (3625, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_igq1.tdf (30260, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_iss3.tdf (3626, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_jss3.tdf (3598, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_kgq1.tdf (55052, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_kss3.tdf (3599, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_lgq1.tdf (51075, 2010-03-02)
5.1 PCF8563\Verilog\db\altsyncram_lss3.tdf (3612, 2010-03-01)
5.1 PCF8563\Verilog\db\altsyncram_mgq1.tdf (62735, 2010-03-02)
5.1 PCF8563\Verilog\db\altsyncram_mss3.tdf (3599, 2010-03-01)
... ...
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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