PipelineCPU2
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：754KB
下载次数：16
上传日期：2012-04-04 11:23:17
上 传 者：
guagualvcha1
说明： Modulsim下Verilog写的五级流水线32位简易CPU
(five level pipeline CPU written in Verilog.)
文件列表:
PipelineCPU2\ALU.v (2599, 2011-12-16)
PipelineCPU2\ALU.v.bak (2599, 2011-12-16)
PipelineCPU2\ALU_tb.v (1899, 2011-12-16)
PipelineCPU2\ALU_tb.v.bak (1917, 2011-12-16)
PipelineCPU2\Decode.v (8677, 2011-12-09)
PipelineCPU2\Decode.v.bak (8672, 2011-12-09)
PipelineCPU2\DecodeSim.v (1875, 2011-11-25)
PipelineCPU2\Decode_tb.v (1772, 2011-12-16)
PipelineCPU2\Decode_tb.v.bak (1847, 2011-12-16)
PipelineCPU2\EX.v (1988, 2011-12-09)
PipelineCPU2\EX.v.bak (1988, 2011-12-09)
PipelineCPU2\ID.v (2868, 2011-12-09)
PipelineCPU2\ID.v.bak (2862, 2011-11-25)
PipelineCPU2\IF.v (1230, 2011-12-16)
PipelineCPU2\IF.v.bak (1229, 2011-12-09)
PipelineCPU2\IF2.v (1284, 2011-12-16)
PipelineCPU2\IF_tb.v (1552, 2011-12-16)
PipelineCPU2\InstructionROM.v (617, 2011-12-16)
PipelineCPU2\InstructionROM.v.bak (617, 2011-11-25)
PipelineCPU2\lab28\.lso (6, 2011-12-16)
PipelineCPU2\lab28\ALU.v (2539, 2011-12-09)
PipelineCPU2\lab28\DataRAM.asy (510, 2011-12-16)
PipelineCPU2\lab28\DataRAM.ngc (10037, 2011-12-16)
PipelineCPU2\lab28\DataRAM.sym (835, 2011-12-16)
PipelineCPU2\lab28\DataRAM.v (3916, 2011-12-16)
PipelineCPU2\lab28\DataRAM.veo (3037, 2011-12-16)
PipelineCPU2\lab28\DataRAM.vhd (4541, 2011-12-16)
PipelineCPU2\lab28\DataRAM.vho (3499, 2011-12-16)
PipelineCPU2\lab28\DataRAM.xco (1780, 2011-12-16)
PipelineCPU2\lab28\DataRAM_flist.txt (177, 2011-12-16)
PipelineCPU2\lab28\DataRAM_xmdf.tcl (3000, 2011-12-16)
PipelineCPU2\lab28\Decode.v (8677, 2011-12-09)
PipelineCPU2\lab28\DecodeSim.v (1875, 2011-11-25)
PipelineCPU2\lab28\EX.v (1988, 2011-12-09)
PipelineCPU2\lab28\ID.v (2868, 2011-12-09)
PipelineCPU2\lab28\IF.v (1229, 2011-12-09)
PipelineCPU2\lab28\InstructionROM.v (617, 2011-11-25)
PipelineCPU2\lab28\lab28.ise (300572, 2011-12-16)
PipelineCPU2\lab28\lab28.ise_ISE_Backup (300572, 2011-12-16)
... ...
The following files were generated for 'DataRAM' in directory
D:\PipelineCPU2\lab28:
DataRAM.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
DataRAM.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
DataRAM.sym:
Please see the core data sheet.
DataRAM.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
DataRAM.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
DataRAM.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
DataRAM.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
DataRAM.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
DataRAM_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
DataRAM_readme.txt:
Text file indicating the files generated and how they are used.
DataRAM_xmdf.tcl:
Please see the core data sheet.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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