array(4) { [0]=> string(46) "dds\Decimation (signal processing) - Wikipedia" [1]=> string(26) " the free encyclopedia.htm" [2]=> string(6) " 25059" [3]=> string(21) " 2012-04-12 11:16:0 " } array(4) { [0]=> string(38) "dds\Digital down converter - Wikipedia" [1]=> string(26) " the free encyclopedia.htm" [2]=> string(6) " 26449" [3]=> string(21) " 2012-04-12 11:02:5 " } array(4) { [0]=> string(28) "dds\Downsampling - Wikipedia" [1]=> string(26) " the free encyclopedia.htm" [2]=> string(6) " 41931" [3]=> string(21) " 2012-04-12 11:08:4 " } array(4) { [0]=> string(50) "dds\Nyquist–Shannon sampling theorem - Wikipedia" [1]=> string(26) " the free encyclopedia.htm" [2]=> string(7) " 129558" [3]=> string(21) " 2012-04-12 11:12:5 " } dds 联合开发网 - pudn.com
dds

所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:3916KB
下载次数:3
上传日期:2012-04-12 15:42:39
上 传 者balashyamu@gmail.c
说明:  the fir filter for digital design synthesizer

文件列表:
dds\a450167.pdf (2415786, 2012-04-12)
dds\ddcdemo.pdf (166832, 2012-04-12)
dds\ddc_dec.pdf (356687, 2012-04-12)
dds\Filter2_tb.pdf (20522, 2012-04-12)
dds\fir_dec_n.pdf (242867, 2012-04-12)
dds\fn3288.pdf (266657, 2012-04-12)
dds\MathWorks India - DSP System Toolbox - Implementing the Filter Chain of a Digital Down-Converter in HDL Demo.htm (55130, 2012-04-12)
dds\MontealegreRammig.pdf (1276171, 2012-04-12)
dds\New Text Document.txt (102, 2012-04-12)
dds (0, 2012-04-12)

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