UART
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：423KB
下载次数：33
上传日期：2012-04-12 19:11:56
上 传 者：
panzdguof
说明： verilog写的串口程序，其功能完全最正确，带工程文件
(verilog to write the serial program, its function is completely the right, with the project file)
文件列表:
UART (0, 2012-03-09)
UART\Project (0, 2012-04-12)
UART\Project\Fusion_UART (0, 2012-03-09)
UART\Project\Fusion_UART\component (0, 2012-04-12)
UART\Project\Fusion_UART\constraint (0, 2012-03-09)
UART\Project\Fusion_UART\constraint\uart_test.pdc (824, 2007-10-15)
UART\Project\Fusion_UART\coreconsole (0, 2012-04-12)
UART\Project\Fusion_UART\designer (0, 2012-03-09)
UART\Project\Fusion_UART\designer\impl1 (0, 2012-03-09)
UART\Project\Fusion_UART\designer\impl1\designer.log (8996, 2007-10-15)
UART\Project\Fusion_UART\designer\impl1\designer_genhdl.log (7810, 2007-08-19)
UART\Project\Fusion_UART\designer\impl1\simulation (0, 2012-04-12)
UART\Project\Fusion_UART\designer\impl1\uart_test.adb (189952, 2007-10-15)
UART\Project\Fusion_UART\designer\impl1\uart_test.dtf (0, 2012-03-09)
UART\Project\Fusion_UART\designer\impl1\uart_test.dtf\verify.log (233, 2007-10-15)
UART\Project\Fusion_UART\designer\impl1\uart_test.ide_des (667, 2007-10-15)
UART\Project\Fusion_UART\designer\impl1\uart_test.pdb (84480, 2007-10-15)
UART\Project\Fusion_UART\designer\impl1\uart_test.pdb.depends (0, 2007-10-15)
UART\Project\Fusion_UART\designer\impl1\uart_test.stp (62204, 2007-10-15)
UART\Project\Fusion_UART\designer\impl1\uart_test.tcl (174, 2007-10-15)
UART\Project\Fusion_UART\designer\impl1\uart_test_ba.sdf (129603, 2007-10-15)
UART\Project\Fusion_UART\designer\impl1\uart_test_ba.v (48030, 2007-10-15)
UART\Project\Fusion_UART\hdl (0, 2012-03-09)
UART\Project\Fusion_UART\hdl\hdlsynchk.tcl (124, 2007-12-11)
UART\Project\Fusion_UART\hdl\rec.v (2572, 2007-07-31)
UART\Project\Fusion_UART\hdl\send.v (2251, 2007-07-31)
UART\Project\Fusion_UART\hdl\uart_test.v (1385, 2011-04-07)
UART\Project\Fusion_UART\phy_synthesis (0, 2012-04-12)
UART\Project\Fusion_UART\simulation (0, 2012-03-09)
UART\Project\Fusion_UART\simulation\meminit.dat (2816, 2007-10-15)
UART\Project\Fusion_UART\simulation\modelsim.ini (264, 2011-04-07)
UART\Project\Fusion_UART\simulation\modelsim.ini.sav (222, 2007-12-17)
UART\Project\Fusion_UART\smartgen (0, 2012-03-09)
UART\Project\Fusion_UART\smartgen\smartgen.aws (364, 2011-04-07)
UART\Project\Fusion_UART\stimulus (0, 2012-03-09)
UART\Project\Fusion_UART\stimulus\BtimErrors.log (20, 2007-07-31)
UART\Project\Fusion_UART\stimulus\files_to_build.txt (26, 2007-07-31)
UART\Project\Fusion_UART\stimulus\hdlsynchk.tcl (107, 2007-07-31)
UART\Project\Fusion_UART\stimulus\uart_test.dsk (996, 2007-07-31)
UART\Project\Fusion_UART\stimulus\uart_test.hpj (890, 2007-07-31)
... ...
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