pipeline_code
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：15KB
下载次数：24
上传日期：2012-04-23 23:36:40
上 传 者：
sktz_whj
说明： 实现了MIPS五级流水CPU,用verilog语言实现
(MIPS CPU verilog)
文件列表:
27组流水线code (0, 2012-01-07)
27组流水线code\abnormity control.v (1292, 2011-12-22)
27组流水线code\adder.v (278, 2011-12-15)
27组流水线code\ALU.v (1087, 2011-12-21)
27组流水线code\ALU_ctr.v (515, 2011-12-16)
27组流水线code\Control_Conflict.v (4748, 2011-12-20)
27组流水线code\CU.v (4600, 2011-12-22)
27组流水线code\data_memory.v (1476, 2011-12-20)
27组流水线code\divider.v (5360, 2011-12-22)
27组流水线code\divider_unit.v (329, 2011-12-21)
27组流水线code\extend.v (495, 2011-12-15)
27组流水线code\extend26.v (286, 2011-12-15)
27组流水线code\EX_MEM.v (1674, 2011-12-21)
27组流水线code\Forwording_unit.v (1444, 2011-12-20)
27组流水线code\GR.v (4795, 2011-12-21)
27组流水线code\ID_EX.v (1487, 2011-12-21)
27组流水线code\IF_ID.v (921, 2011-12-22)
27组流水线code\Ins_Mem.v (322, 2011-12-22)
27组流水线code\KD_Pipeline.v (7219, 2011-12-22)
27组流水线code\LOAD_USE.v (1157, 2011-12-22)
27组流水线code\MEM_WB.v (1134, 2011-12-20)
27组流水线code\mux2.v (385, 2011-12-20)
27组流水线code\mux4.v (530, 2011-12-15)
27组流水线code\pc.v (494, 2011-12-15)
27组流水线code\PC_adder.v (345, 2011-12-14)
27组流水线code\pc_reg.v (487, 2011-12-22)
27组流水线code\testbanch.v (2173, 2011-12-22)
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