DDR-SDRAM
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：876KB
下载次数：23
上传日期：2012-05-02 00:01:38
上 传 者：
ziyingpiaofei
说明： DDR SDRAM的设计，包括DDR SDRAM控制器，以及Modelsim仿真
(The design of DDR SDRAM, DDR SDRAM controller, and Modelsim simulation)
文件列表:
DDR SDRAM\doc\ddr_sdram.pdf (472801, 2000-05-30)
DDR SDRAM\model\mt46v4m16.vhd (43490, 1999-11-08)
DDR SDRAM\model\mti_pkg.vhd (4932, 2000-08-14)
DDR SDRAM\route\ddr_sdram.csf (92655, 2001-04-11)
DDR SDRAM\route\ddr_sdram.esf (732, 2001-04-11)
DDR SDRAM\route\ddr_sdram.psf (2371, 2001-04-11)
DDR SDRAM\route\ddr_sdram.quartus (193, 2000-08-14)
DDR SDRAM\route\ddr_sdram.vqm (603177, 2000-06-30)
DDR SDRAM\route\pll1.vhd (5081, 2000-06-29)
DDR SDRAM\simulation\APEX20KE_MF.VHD (42715, 2000-06-29)
DDR SDRAM\simulation\ddr_command.vhd (17418, 2000-08-14)
DDR SDRAM\simulation\ddr_control_interface.vhd (9161, 2000-08-14)
DDR SDRAM\simulation\ddr_data_path.vhd (9286, 2000-08-14)
DDR SDRAM\simulation\ddr_sdram.vhd (18307, 2000-08-14)
DDR SDRAM\simulation\ddr_sdram_tb.vhd (24245, 2000-08-14)
DDR SDRAM\simulation\io_utils.vhd (8703, 1998-01-16)
DDR SDRAM\simulation\lpm_pack.vhd (22051, 1999-10-22)
DDR SDRAM\simulation\modelsim.ini (8116, 2000-08-14)
DDR SDRAM\simulation\mt46v4m16.vhd (43490, 1999-11-08)
DDR SDRAM\simulation\mti_pkg.bak (4932, 1999-11-08)
DDR SDRAM\simulation\mti_pkg.vhd (4932, 2000-08-14)
DDR SDRAM\simulation\pll1.vhd (5081, 2000-06-29)
DDR SDRAM\simulation\stdlogar.vhd (68654, 1998-01-16)
DDR SDRAM\simulation\util1164.vhd (3310, 1998-01-16)
DDR SDRAM\simulation\wave.do (5967, 2000-08-14)
DDR SDRAM\simulation\work\altcam\behave.dat (7970, 2000-08-14)
DDR SDRAM\simulation\work\altcam\behave.psm (69568, 2000-08-14)
DDR SDRAM\simulation\work\altcam\_primary.dat (5972, 2000-08-14)
DDR SDRAM\simulation\work\altclklock\behavior.dat (2016, 2000-08-14)
DDR SDRAM\simulation\work\altclklock\behavior.psm (12360, 2000-08-14)
DDR SDRAM\simulation\work\altclklock\_primary.dat (799, 2000-08-14)
DDR SDRAM\simulation\work\altlvds_rx\behavior.dat (3122, 2000-08-14)
DDR SDRAM\simulation\work\altlvds_rx\behavior.psm (14800, 2000-08-14)
DDR SDRAM\simulation\work\altlvds_rx\_primary.dat (563, 2000-08-14)
DDR SDRAM\simulation\work\altlvds_tx\behavior.dat (1868, 2000-08-14)
DDR SDRAM\simulation\work\altlvds_tx\behavior.psm (9720, 2000-08-14)
DDR SDRAM\simulation\work\altlvds_tx\_primary.dat (598, 2000-08-14)
DDR SDRAM\simulation\work\command\rtl.dat (4679, 2000-06-28)
... ...
File/Directory Description
=============================================================================
\doc DDR SDRAM reference design documentation
\model Contains the vhdl SDRAM model
\route Contains the Quartus 2000.05 project files a routed controller design
\simulation Contains the vhdl testbench, modelsim project file, and library
\source Contains the vhdl source files for the DDR SDRAM reference design
\synthesis\synplicity Contains all synplicity project files associated with synthesizing the reference design
Version History
===============
v1.0 First release
v1.0.1 Updates to csf/esf/psf constraint files in \route to correct pin conflict on U3.
近期下载者：
相关文件：
收藏者：