Two_Port_RAM
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：2033KB
下载次数：17
上传日期：2012-05-06 17:26:40
上 传 者：
gdlhh2010
说明： 双端口的ROM verilog实现,基于Actel的开发开发平台
(Double port ROM verilog realization, based on the development of the Actel development platform)
文件列表:
Two_Port_RAM\Two Port RAM实验例程.pdf (1669916, 2007-11-13)
Two_Port_RAM\TwoPortRAM\designer\impl1\designer.log (474, 2007-11-13)
Two_Port_RAM\TwoPortRAM\designer\impl1\tp_ram_top\projectData\tp_ram_top.stp (69753, 2007-06-30)
Two_Port_RAM\TwoPortRAM\designer\impl1\tp_ram_top\tp_ram_top.log (6199, 2007-06-30)
Two_Port_RAM\TwoPortRAM\designer\impl1\tp_ram_top\tp_ram_top.pro (1553, 2007-11-13)
Two_Port_RAM\TwoPortRAM\designer\impl1\tp_ram_top.adb (323072, 2007-11-13)
Two_Port_RAM\TwoPortRAM\designer\impl1\tp_ram_top.dtf\verify.log (233, 2007-06-30)
Two_Port_RAM\TwoPortRAM\designer\impl1\tp_ram_top.ide_des (690, 2007-11-13)
Two_Port_RAM\TwoPortRAM\designer\impl1\tp_ram_top.stp (69753, 2007-06-30)
Two_Port_RAM\TwoPortRAM\designer\impl1\tp_ram_top.tcl (175, 2007-11-13)
Two_Port_RAM\TwoPortRAM\hdl\ctrl_RAM.v (5133, 2007-06-30)
Two_Port_RAM\TwoPortRAM\hdl\hdlsynchk.tcl (140, 2007-06-30)
Two_Port_RAM\TwoPortRAM\hdl\rec.v (2885, 2007-06-25)
Two_Port_RAM\TwoPortRAM\hdl\send.v (2474, 2007-06-25)
Two_Port_RAM\TwoPortRAM\hdl\tp_ram_top.v (1780, 2007-06-30)
Two_Port_RAM\TwoPortRAM\simulation\meminit.dat (2816, 2007-11-13)
Two_Port_RAM\TwoPortRAM\simulation\modelsim.ini (223, 2007-11-13)
Two_Port_RAM\TwoPortRAM\simulation\modelsim.ini.sav (230, 2007-10-22)
Two_Port_RAM\TwoPortRAM\simulation\ram25608_R0C0.mem (2816, 2007-11-13)
Two_Port_RAM\TwoPortRAM\smartgen\ram25608\ram25608.cxf (1128, 2007-06-24)
Two_Port_RAM\TwoPortRAM\smartgen\ram25608\ram25608.gen (611, 2007-06-24)
Two_Port_RAM\TwoPortRAM\smartgen\ram25608\ram25608.log (2120, 2007-06-24)
Two_Port_RAM\TwoPortRAM\smartgen\ram25608\ram25608.shx (0, 2007-06-24)
Two_Port_RAM\TwoPortRAM\smartgen\ram25608\ram25608.v (2560, 2007-06-24)
Two_Port_RAM\TwoPortRAM\smartgen\ram25608\ram25608_R0C0.mem (2816, 2007-06-24)
Two_Port_RAM\TwoPortRAM\smartgen\ram25608_work.ixf (1455, 2007-06-30)
Two_Port_RAM\TwoPortRAM\smartgen\smartgen.aws (562, 2007-11-13)
Two_Port_RAM\TwoPortRAM\synthesis\.recordref (0, 2007-06-30)
Two_Port_RAM\TwoPortRAM\synthesis\stdout.log (1628, 2007-06-30)
Two_Port_RAM\TwoPortRAM\synthesis\syntmp\sap.log (743, 2007-06-30)
Two_Port_RAM\TwoPortRAM\synthesis\syntmp\tp_ram_top.msg (2355, 2007-06-30)
Two_Port_RAM\TwoPortRAM\synthesis\syntmp\tp_ram_top.plg (468, 2007-06-30)
Two_Port_RAM\TwoPortRAM\synthesis\syntmp\tp_ram_top_flink.htm (372, 2007-06-30)
Two_Port_RAM\TwoPortRAM\synthesis\syntmp\tp_ram_top_srr.htm (37290, 2007-06-30)
Two_Port_RAM\TwoPortRAM\synthesis\syntmp\tp_ram_top_toc.htm (1218, 2007-06-30)
Two_Port_RAM\TwoPortRAM\synthesis\tp_ram_top.areasrr (7123, 2007-06-30)
Two_Port_RAM\TwoPortRAM\synthesis\tp_ram_top.edn (245776, 2007-06-30)
Two_Port_RAM\TwoPortRAM\synthesis\tp_ram_top.fse (0, 2007-06-30)
Two_Port_RAM\TwoPortRAM\synthesis\tp_ram_top.htm (344, 2007-06-30)
Two_Port_RAM\TwoPortRAM\synthesis\tp_ram_top.map (0, 2007-06-30)
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