Static-PLL
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：2519KB
下载次数：27
上传日期：2012-05-06 18:52:00
上 传 者：
gdlhh2010
说明： 基于Actel开发平台的静态锁相环设计，verilog实现
(Actel development platform based on the static PLL design, verilog realized)
文件列表:
Static PLL\Static PLL实验例程.pdf (1967472, 2007-11-13)
Static PLL\Static_PLL_lab.rar (1391, 2007-06-29)
Static PLL\Stc_PLL\designer\impl1\designer.log (8067, 2011-04-25)
Static PLL\Stc_PLL\designer\impl1\designer_gen_ba.log (473, 2007-06-29)
Static PLL\Stc_PLL\designer\impl1\designer_synth_check.log (1333, 2011-04-25)
Static PLL\Stc_PLL\designer\impl1\flashpro.log (0, 2007-06-29)
Static PLL\Stc_PLL\designer\impl1\PLL_top.adb (70144, 2007-11-13)
Static PLL\Stc_PLL\designer\impl1\PLL_top.dtf\PLL_top\$$FlashPro_FPBBALTLPT1.L$$ (780, 2007-06-29)
Static PLL\Stc_PLL\designer\impl1\PLL_top.dtf\PLL_top\PLL_top.log (1075, 2007-06-29)
Static PLL\Stc_PLL\designer\impl1\PLL_top.dtf\PLL_top\PLL_top.pro (1580, 2011-04-25)
Static PLL\Stc_PLL\designer\impl1\PLL_top.dtf\PLL_top\projectData\PLL_top.stp (42960, 2007-06-29)
Static PLL\Stc_PLL\designer\impl1\PLL_top.dtf\verify.log (233, 2007-11-13)
Static PLL\Stc_PLL\designer\impl1\PLL_top.ide_des (723, 2011-04-25)
Static PLL\Stc_PLL\designer\impl1\PLL_top.pdb (41472, 2007-11-13)
Static PLL\Stc_PLL\designer\impl1\PLL_top.pdb.depends (0, 2007-11-13)
Static PLL\Stc_PLL\designer\impl1\PLL_top.stp (42960, 2007-06-29)
Static PLL\Stc_PLL\designer\impl1\PLL_top.tcl (1600, 2011-04-25)
Static PLL\Stc_PLL\designer\impl1\PLL_top_1.adb (28672, 2011-04-25)
Static PLL\Stc_PLL\designer\impl1\PLL_top_1.ide_des (738, 2011-04-25)
Static PLL\Stc_PLL\designer\impl1\PLL_top_ba.sdf (11456, 2007-06-29)
Static PLL\Stc_PLL\designer\impl1\PLL_top_ba.v (5381, 2007-06-29)
Static PLL\Stc_PLL\designer\impl1\Static_PLL.ide_des (200, 2011-04-25)
Static PLL\Stc_PLL\hdl\ctrl_PLL.v (1832, 2007-06-29)
Static PLL\Stc_PLL\hdl\hdlsynchk.tcl (130, 2007-06-29)
Static PLL\Stc_PLL\hdl\PLL_top.v (2287, 2007-06-29)
Static PLL\Stc_PLL\simulation\meminit.dat (2816, 2007-11-13)
Static PLL\Stc_PLL\simulation\modelsim.ini (295, 2011-04-25)
Static PLL\Stc_PLL\simulation\modelsim.ini.sav (291, 2011-04-25)
Static PLL\Stc_PLL\simulation\modelsim.log (2810, 2007-06-29)
Static PLL\Stc_PLL\simulation\presynth\@p@l@l_top\verilog.psm (4760, 2007-06-29)
Static PLL\Stc_PLL\simulation\presynth\@p@l@l_top\_primary.dat (555, 2007-06-29)
Static PLL\Stc_PLL\simulation\presynth\@p@l@l_top\_primary.vhd (520, 2007-06-29)
Static PLL\Stc_PLL\simulation\presynth\@static_@p@l@l\verilog.psm (6369, 2007-06-29)
Static PLL\Stc_PLL\simulation\presynth\@static_@p@l@l\_primary.dat (2162, 2007-06-29)
Static PLL\Stc_PLL\simulation\presynth\@static_@p@l@l\_primary.vhd (440, 2007-06-29)
Static PLL\Stc_PLL\simulation\presynth\ctrl_@p@l@l\verilog.psm (9229, 2007-06-29)
Static PLL\Stc_PLL\simulation\presynth\ctrl_@p@l@l\_primary.dat (798, 2007-06-29)
Static PLL\Stc_PLL\simulation\presynth\ctrl_@p@l@l\_primary.vhd (221, 2007-06-29)
Static PLL\Stc_PLL\simulation\presynth\stimulus\verilog.psm (34446, 2007-06-29)
Static PLL\Stc_PLL\simulation\presynth\stimulus\_primary.dat (2719, 2007-06-29)
... ...
近期下载者：
相关文件：
收藏者：