exercise_4.2
所属分类：VHDL/FPGA/Verilog
开发工具：LabView
文件大小：209KB
下载次数：15
上传日期：2012-05-08 16:05:08
上 传 者：
taoufik_10
说明： spartan 3E programming fpga module for signal processing
文件列表:
exercise_4.2\Exercise 42.aliases (78, 2007-12-05)
exercise_4.2\Exercise 42.lvproj (28757, 2007-11-29)
exercise_4.2\FPGA Bitfiles\Exercise 42.lvproj_FPGA Target 2_Two Loops FIFOs.vi.lvbit (289328, 2007-11-29)
exercise_4.2\FPGA Bitfiles\Exercise 42.lvproj_FPGA Target_Two Loops FIFOs.vi.lvbit (515549, 2007-10-02)
exercise_4.2\Two Loops FIFOs.vi (107879, 2007-11-29)
exercise_4.2\Two Loops FIFOs_Spartan3E.vi (108105, 2007-11-26)
exercise_4.2\FPGA Bitfiles (0, 2007-11-29)
exercise_4.2 (0, 2007-12-05)
This is the solution to Excercise 2.1
NOTE: The FPGA VI was compiled for PCI-7831R target. For all other target, create a new project for the target and then recompile.
(1) Open the Exercise 42.lvproj
(2) Open Two Loops FIFOs.VI to view the completed FPGA VI
(3) Compile and run the FPGA Vi.
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