exercise_5.1
所属分类：VHDL/FPGA/Verilog
开发工具：LabView
文件大小：299KB
下载次数：10
上传日期：2012-05-08 16:06:58
上 传 者：
taoufik_10
说明： spartan 3e fpga module programming
文件列表:
exercise_5.1\NI_R_Series_Hardware\Exercise 51.aliases (80, 2007-11-29)
exercise_5.1\NI_R_Series_Hardware\Exercise 51.lvproj (15843, 2007-10-02)
exercise_5.1\NI_R_Series_Hardware\FPGA Bitfiles\Exercise 51.lvproj_FPGA Target_Simple AIAO (FPGA)~D2.lvbit (515274, 2007-10-02)
exercise_5.1\NI_R_Series_Hardware\Simple AIAO (FPGA).vi (2789790, 2007-10-01)
exercise_5.1\NI_R_Series_Hardware\Simple AIAO (Host).vi (106942, 2007-10-02)
exercise_5.1\Spartan_3E\example 3.aliases (48, 2007-11-29)
exercise_5.1\Spartan_3E\example 3.lvproj (15610, 2007-11-28)
exercise_5.1\Spartan_3E\FPGA Bitfiles\example 3.lvproj_FPGA Target_FPGA.vi.lvbit (288422, 2007-11-28)
exercise_5.1\Spartan_3E\FPGA Host.vi (60549, 2007-11-28)
exercise_5.1\Spartan_3E\FPGA.vi (63308, 2007-11-28)
exercise_5.1\NI_R_Series_Hardware\FPGA Bitfiles (0, 2007-11-26)
exercise_5.1\Spartan_3E\FPGA Bitfiles (0, 2007-11-28)
exercise_5.1\NI_R_Series_Hardware (0, 2007-11-29)
exercise_5.1\Spartan_3E (0, 2007-11-29)
exercise_5.1 (0, 2007-11-29)
This is the solution to Excercise 5.1
NOTE: The FPGA VI was compiled for PCI-7831R target. For all other target, create a new project for the target and then recompile.
(1) Open the Exercise 51.lvproj
(2) Open Simple AIAO (FPGA).VI to view the completed FPGA VI
(3) Open Simple AIAO (Host).VI to view the competed Host interface VI
(4) Compile the FPGA Vi.
(5) Run the Host VI
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