说明：  基于CPLD的VHDL语言数字钟(含秒表)设计及程序 利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。所有数字逻辑功能都在CPLD器件上用VHDL语言实现。这样设计具有体积小、设计周期短（设计过程中即可实现时序仿真）、调试方便、故障率低、修改升级容易等特点。
(The VHDL language based on CPLD digital clock (including a stopwatch) design and program By using a chips in addition to clock source, buttons, the speaker and displays (digital tube) all the digital circuit function outside. All digital logic function in with VHDL language CPLD device realized. This design has small, the design cycle short (design process can be realized in the temporal simulation), convenient debug, low failure rate, modify upgrade easily etc. Characteristics. )