文件列表:

xapp518\config (0, 2011-08-10)
xapp518\config\bitfile (0, 2011-09-23)
xapp518\config\bitfile\PCIe_ISP_top.bit (2285305, 2012-02-15)
xapp518\config\PROM (0, 2011-09-23)
xapp518\config\PROM\XAPP518_PROM_img.mcs (25968662, 2011-06-30)
xapp518\hw (0, 2012-02-15)
xapp518\hw\src (0, 2012-02-16)
xapp518\hw\src\xilinx_pcie_2_0_ep_v6.v (19378, 2012-02-16)
xapp518\hw\src\PCIe_ISP_top.v (5436, 2012-02-16)
xapp518\hw\src\programmer (0, 2012-02-16)
xapp518\hw\src\programmer\programmer.v (21722, 2012-02-16)
xapp518\hw\src\programmer\programmer.v.bak (21751, 2012-02-15)
xapp518\hw\src\PIO (0, 2012-02-15)
xapp518\hw\src\PIO\data_transfer.v (5656, 2011-08-16)
xapp518\hw\src\PIO\pci_exp_8_lane_64b_ep.v (12537, 2010-11-16)
xapp518\hw\src\PIO\pcie_app_v6.v (12281, 2011-06-22)
xapp518\hw\src\PIO\PIO.v (8787, 2011-08-16)
xapp518\hw\src\PIO\PIO_64.v (2682, 2010-11-16)
xapp518\hw\src\PIO\PIO_64_RX_ENGINE.v (19161, 2010-11-16)
xapp518\hw\src\PIO\PIO_64_TX_ENGINE.v (9515, 2010-11-16)
xapp518\hw\src\PIO\PIO_EP.v (11844, 2011-08-16)
xapp518\hw\src\PIO\PIO_EP_MEM_ACCESS.v (9829, 2011-02-23)
xapp518\hw\src\PIO\PIO_TO_CTRL.v (3974, 2010-11-16)
xapp518\hw\src\PCIe (0, 2012-02-15)
xapp518\hw\src\PCIe\gtx_drp_chanalign_fix_3752_v6.v (6942, 2012-02-13)
xapp518\hw\src\PCIe\gtx_rx_valid_filter_v6.v (12103, 2012-02-13)
xapp518\hw\src\PCIe\gtx_tx_sync_rate_v6.v (14596, 2012-02-13)
xapp518\hw\src\PCIe\gtx_wrapper_v6.v (26511, 2012-02-13)
xapp518\hw\src\PCIe\pcie_2_0_v6.v (82207, 2012-02-13)
xapp518\hw\src\PCIe\pcie_bram_top_v6.v (6038, 2012-02-13)
xapp518\hw\src\PCIe\pcie_bram_v6.v (11739, 2012-02-13)
xapp518\hw\src\PCIe\pcie_brams_v6.v (8684, 2012-02-13)
xapp518\hw\src\PCIe\pcie_clocking_v6.v (11852, 2012-02-13)
xapp518\hw\src\PCIe\pcie_gtx_v6.v (24312, 2012-02-13)
xapp518\hw\src\PCIe\pcie_pipe_lane_v6.v (12792, 2012-02-13)
xapp518\hw\src\PCIe\pcie_pipe_misc_v6.v (7726, 2012-02-13)
xapp518\hw\src\PCIe\pcie_pipe_v6.v (36367, 2012-02-13)
xapp518\hw\src\PCIe\pcie_reset_delay_v6.v (4060, 2012-02-13)
xapp518\hw\src\PCIe\pcie_upconfig_fix_3451_v6.v (7377, 2012-02-13)
... ...

************************************************************************* ____ ____ / /\/ / /___/ \ / \ \ \/ Copyright 2012 Xilinx, Inc. All rights reserved. \ \ This file contains confidential and proprietary / / information of Xilinx, Inc. and is protected under U.S. /___/ /\ and international copyright and other intellectual \ \ / \ property laws. \___\/\___\ ************************************************************************* Vendor: Xilinx Current readme.txt Version: 1.0 Date Last Modified: 03/30/12 Date Created: 03/30/12 Associated Filename: xapp518.zip Associated Document: XAPP518: In-System Programming of BPI PROM for Virtex-6 FPGAs Using PCI Express Technology Supported Device(s): XC6VLX240TFF1156-1 ************************************************************************* Disclaimer: This disclaimer is not a license and does not grant any rights to the materials distributed herewith. Except as otherwise provided in a valid license issued to you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under or in connection with these materials, including for any direct, or any indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Critical Applications: Xilinx products are not designed or intended to be fail-safe, or for use in any application requiring fail-safe performance, such as life-support or safety devices or systems, Class III medical devices, nuclear facilities, applications related to the deployment of airbags, or any other applications that could lead to death, personal injury, or severe property or environmental damage (individually and collectively, "Critical Applications"). Customer assumes the sole risk and liability of any use of Xilinx products in Critical Applications, subject only to applicable laws and regulations governing limitations on product liability. THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. ************************************************************************* This readme file contains these sections: 1. REVISION HISTORY 2. OVERVIEW 3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS 4. DESIGN FILE HIERARCHY 5. INSTALLATION AND OPERATING INSTRUCTIONS 6. OTHER INFORMATION (OPTIONAL) 7. SUPPORT 1. REVISION HISTORY Readme Date Version Revision Description ========================================================================= 12/06/11 Early Access Initial early release. 03/30/12 1.0 Initial Xilinx release. ========================================================================= 2. OVERVIEW This readme describes how to use the reference design files that come with XAPP518. The reference design zip file contains the following design files: * XAPP518 reference design source codes (Verilog only) * Jungo driver binary system files * ISE project files * pre-built demo files 3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS * ML605 rev. D demonstration board (XC6VLX240T-FF1156 production device) * Xilinx ISE 13.4 or higher. * Modelsim SE 6.5b * X86 system with Windows XP Service Pack 3 installed 4. DESIGN FILE HIERARCHY The directory structure underneath this top-level folder is described below: \config | This folder contains the demo configuration files | +----- \bitfiles | The demo FPGA bitfile PCIe_ISP_top.bit is found here. | | +----- \PROM | XAPP518_PROM_img.mcs is the demo PROM MCS file used to be programmed | to the target PROM. | \hw | This folder contains the source codes and ISE project | +----- \ISE | This folder has the ISE13.4 project file | +----- \src | This folder has all the source files to build the design | \sw | This folder contains the source codes and executable of the XAPP518 demo application. | It also has the Jungo driver files. 5. INSTALLATION AND OPERATING INSTRUCTIONS See XAPP518 for detailed description on installing and running the demo. 6. OTHER INFORMATION * This reference design does not provide the Jungo driver source codes. (See Answer Record 31416.) Contact Jungo directly for source code availability (http://www.jungo.com/). * To quick run the demo without building the project, refer to the reference Design Demonstration section in XAPP518. * Known Issues - See appnote 7. SUPPORT To obtain technical support for this reference design, go to www.xilinx.com/support to locate answers to known issues in the Xilinx Answers Database or to create a WebCase.

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