hdlsrc

所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:15KB
下载次数:10
上传日期:2012-05-29 12:33:30
上 传 者brittoparianna
说明:  ofdm transceiver code

文件列表:
hdlsrc\AWGN_Channel.vhd (1092, 2012-05-22)
hdlsrc\Bernoulli_Binary_Generator.vhd (1480, 2012-05-22)
hdlsrc\decoder.vhd (1851, 2012-05-22)
hdlsrc\deinterleaver.vhd (1503, 2012-05-22)
hdlsrc\Fec_coder.vhd (1527, 2012-05-22)
hdlsrc\Interleaver.vhd (1618, 2012-05-22)
hdlsrc\m4.vhd (5054, 2012-05-22)
hdlsrc\m4_compile.do (380, 2012-05-22)
hdlsrc\m4_map.txt (631, 2012-05-22)
hdlsrc\m4_synplify.tcl (579, 2012-05-22)
hdlsrc\Matrix_Deinterleaver.vhd (986, 2012-05-22)
hdlsrc\Matrix_Interleaver.vhd (970, 2012-05-22)
hdlsrc\QAM_demapping.vhd (1074, 2012-05-22)
hdlsrc\QAM_mapping.vhd (1702, 2012-05-22)
hdlsrc\Subsystem.vhd (1451, 2012-05-22)
hdlsrc\Subsystem1.vhd (1587, 2012-05-22)
hdlsrc\Subsystem_block.vhd (1648, 2012-05-22)
hdlsrc\transcript (766, 2012-05-22)
hdlsrc\Unipolar_to_Bipolar_Converter.vhd (1995, 2012-05-22)
hdlsrc\vsim.wlf (32768, 2012-05-22)
hdlsrc\work\awgn_channel\rtl.dat (272, 2012-05-22)
hdlsrc\work\awgn_channel\rtl.dbs (578, 2012-05-22)
hdlsrc\work\awgn_channel\rtl.prw (945, 2012-05-22)
hdlsrc\work\awgn_channel\rtl.psm (3352, 2012-05-22)
hdlsrc\work\awgn_channel\_primary.dat (200, 2012-05-22)
hdlsrc\work\awgn_channel\_primary.dbs (469, 2012-05-22)
hdlsrc\work\_info (609, 2012-05-22)
hdlsrc\work\_vmake (26, 2012-05-22)
hdlsrc\work\awgn_channel (0, 2012-05-22)
hdlsrc\work\_temp (0, 2012-05-22)
hdlsrc\work (0, 2012-05-22)
hdlsrc (0, 2012-05-25)

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