music_player
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：5264KB
下载次数：77
上传日期：2012-06-02 04:53:10
上 传 者：
ericzyq
说明： 用verilog编写的音乐播放器，内置3首歌
(Music player written in Verilog, built-in 3-song)
文件列表:
lab28_new\PipelineCPU\ISE\DataRAM.mif (544, 2011-12-16)
lab28_new\PipelineCPU\ISE\DataRAM.ngc (10182, 2011-12-16)
lab28_new\PipelineCPU\ISE\DataRAM.sym (834, 2011-12-16)
lab28_new\PipelineCPU\ISE\DataRAM.v (4022, 2011-12-16)
lab28_new\PipelineCPU\ISE\DataRAM.veo (3037, 2011-12-16)
lab28_new\PipelineCPU\ISE\DataRAM.vhd (4539, 2011-12-16)
lab28_new\PipelineCPU\ISE\DataRAM.vho (3499, 2011-12-16)
lab28_new\PipelineCPU\ISE\DataRAM.xco (1853, 2011-12-16)
lab28_new\PipelineCPU\ISE\DataRAM_flist.txt (190, 2011-12-16)
lab28_new\PipelineCPU\ISE\DataRAM_xmdf.tcl (3164, 2011-12-16)
lab28_new\PipelineCPU\ISE\MipsPipelineCPU.bld (910, 2011-12-16)
lab28_new\PipelineCPU\ISE\MipsPipelineCPU.cmd_log (2008, 2011-12-16)
lab28_new\PipelineCPU\ISE\MipsPipelineCPU.ise (303055, 2011-12-16)
lab28_new\PipelineCPU\ISE\MipsPipelineCPU.ise_ISE_Backup (303055, 2011-12-16)
lab28_new\PipelineCPU\ISE\MipsPipelineCPU.lso (6, 2011-12-15)
lab28_new\PipelineCPU\ISE\MipsPipelineCPU.ncd (686630, 2011-12-16)
lab28_new\PipelineCPU\ISE\MipsPipelineCPU.ngc (511073, 2011-12-16)
lab28_new\PipelineCPU\ISE\MipsPipelineCPU.ngd (938095, 2011-12-16)
lab28_new\PipelineCPU\ISE\MipsPipelineCPU.ngr (890952, 2011-12-16)
lab28_new\PipelineCPU\ISE\MipsPipelineCPU.ntrc_log (670, 2011-12-16)
lab28_new\PipelineCPU\ISE\MipsPipelineCPU.pad (41119, 2011-12-16)
lab28_new\PipelineCPU\ISE\MipsPipelineCPU.par (6366, 2011-12-16)
lab28_new\PipelineCPU\ISE\MipsPipelineCPU.pcf (318, 2011-12-16)
lab28_new\PipelineCPU\ISE\MipsPipelineCPU.prj (374, 2011-12-16)
lab28_new\PipelineCPU\ISE\MipsPipelineCPU.restore (51414, 2011-12-16)
lab28_new\PipelineCPU\ISE\MipsPipelineCPU.spl (214, 2011-12-16)
lab28_new\PipelineCPU\ISE\MipsPipelineCPU.stx (0, 2011-12-16)
lab28_new\PipelineCPU\ISE\MipsPipelineCPU.sym (2120, 2011-12-16)
lab28_new\PipelineCPU\ISE\MipsPipelineCPU.syr (61529, 2011-12-16)
lab28_new\PipelineCPU\ISE\mipspipelinecpu.twr (14739, 2011-12-16)
lab28_new\PipelineCPU\ISE\mipspipelinecpu.twx (53402, 2011-12-16)
lab28_new\PipelineCPU\ISE\MipsPipelineCPU.unroutes (148, 2011-12-16)
lab28_new\PipelineCPU\ISE\MipsPipelineCPU.xpi (46, 2011-12-16)
lab28_new\PipelineCPU\ISE\MipsPipelineCPU.xst (1181, 2011-12-16)
lab28_new\PipelineCPU\ISE\MipsPipelineCPU_guide.ncd (686630, 2011-12-16)
lab28_new\PipelineCPU\ISE\MipsPipelineCPU_map.map (2961, 2011-12-16)
lab28_new\PipelineCPU\ISE\MipsPipelineCPU_map.mrp (42126, 2011-12-16)
lab28_new\PipelineCPU\ISE\MipsPipelineCPU_map.ncd (317770, 2011-12-16)
lab28_new\PipelineCPU\ISE\MipsPipelineCPU_map.ngm (1686065, 2011-12-16)
... ...
The following files were generated for 'DataRAM' in directory
F:\fpga\lab5\IPCore:
DataRAM.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
DataRAM.mif:
Memory Initialization File which is automatically generated by the
CORE Generator System for some modules when a simulation flow is
specified. A MIF data file is used to support HDL functional
simulation of modules which use arrays of values.
DataRAM.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
DataRAM.sym:
Please see the core data sheet.
DataRAM.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
DataRAM.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
DataRAM.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
DataRAM.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
DataRAM.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
DataRAM_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
DataRAM_readme.txt:
Text file indicating the files generated and how they are used.
DataRAM_xmdf.tcl:
Please see the core data sheet.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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