说明：  vhdl实现FSK调制，本次毕业设计的数据速率 1.2kb/s，要求产生一个1.2kHz的正弦信号，对正弦信号每周期取100个采样点，因此要求产生3个时钟信号：1.2kHz（数据速率）、120kHz（产生1.2kHz正弦信号的输入时钟）、240kHz（产生2.4kHz正弦信号的输入时钟）。基准时钟已由一个外部时钟120MHz提供，要得到前面三种时钟，就需要首先设计一个模50的分频器产生240kHz信号，再设计一个二分频器，生产一个120kHz的信号，然后再前面的基础上再设计一个模100的分频器，用来产生1.2kHz的随机信号产生速率。
(vhdl achieve FSK modulation, the graduate design data rate of 1.2kb/s to produce a sinusoidal signal of 1.2kHz, take the 100 sampling points per cycle of the sinusoidal signal, thus requiring to produce the three clock signals: 1.2 kHz (data rate , 120kHz, a 1.2kHz sine input clock signal), 240kHz (a 2.4kHz sine signal input clock). 120MHz reference clock has been an external clock to get the first three clock, you need to first design a mold 50 of the divider to produce a 240kHz signal, re-design of a two frequency divider to produce a 120kHz signal, and then the front of the base on the re-design of a mold 100 of the divider used to generate the 1.2kHz random signal generator rate.)