03-NEC_2003_C
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：322KB
下载次数：12
上传日期：2012-06-05 22:31:42
上 传 者：
Emily0626
说明： 移相信号发生器（2003年C题），verilog源程序，
(Phase shift generator Problem C (2003), Verilog source code,)
文件列表:
03-移相信号发生器（2003年C题）\dds_test\automake.log (0, 2011-03-09)
03-移相信号发生器（2003年C题）\dds_test\bitgen.ut (518, 2011-03-09)
03-移相信号发生器（2003年C题）\dds_test\core.tpl (1358, 2011-03-08)
03-移相信号发生器（2003年C题）\dds_test\dds_sin.asy (386, 2011-03-08)
03-移相信号发生器（2003年C题）\dds_test\dds_sin.edn (62503, 2011-03-08)
03-移相信号发生器（2003年C题）\dds_test\dds_sin.ngo (25944, 2011-03-08)
03-移相信号发生器（2003年C题）\dds_test\dds_sin.sym (569, 2011-03-08)
03-移相信号发生器（2003年C题）\dds_test\dds_sin.v (3827, 2011-03-08)
03-移相信号发生器（2003年C题）\dds_test\dds_sin.veo (2965, 2011-03-08)
03-移相信号发生器（2003年C题）\dds_test\dds_sin.vhd (3944, 2011-03-08)
03-移相信号发生器（2003年C题）\dds_test\dds_sin.vho (3549, 2011-03-08)
03-移相信号发生器（2003年C题）\dds_test\dds_sin.xco (1156, 2011-03-08)
03-移相信号发生器（2003年C题）\dds_test\dds_sin_flist.txt (181, 2011-03-08)
03-移相信号发生器（2003年C题）\dds_test\dds_sin_TRIG_ROM.mif (16384, 2011-03-08)
03-移相信号发生器（2003年C题）\dds_test\dds_test.dhp (1784, 2011-03-09)
03-移相信号发生器（2003年C题）\dds_test\dds_test.ise (4552, 2011-03-09)
03-移相信号发生器（2003年C题）\dds_test\dds_test.ise_ISE_Backup (4552, 2011-03-09)
03-移相信号发生器（2003年C题）\dds_test\Project.dhp (1198, 2011-03-08)
03-移相信号发生器（2003年C题）\dds_test\topdesign.bgn (5088, 2011-03-09)
03-移相信号发生器（2003年C题）\dds_test\topdesign.bit (167055, 2011-03-09)
03-移相信号发生器（2003年C题）\dds_test\topdesign.bld (815, 2011-03-09)
03-移相信号发生器（2003年C题）\dds_test\topdesign.cmd_log (2272, 2011-03-09)
03-移相信号发生器（2003年C题）\dds_test\topdesign.drc (38, 2011-03-09)
03-移相信号发生器（2003年C题）\dds_test\topdesign.lso (6, 2011-03-09)
03-移相信号发生器（2003年C题）\dds_test\topdesign.mrp (12961, 2011-03-09)
03-移相信号发生器（2003年C题）\dds_test\topdesign.nc1 (37, 2011-03-09)
03-移相信号发生器（2003年C题）\dds_test\topdesign.ncd (50285, 2011-03-09)
03-移相信号发生器（2003年C题）\dds_test\topdesign.ngc (26192, 2011-03-09)
03-移相信号发生器（2003年C题）\dds_test\topdesign.ngd (104173, 2011-03-09)
03-移相信号发生器（2003年C题）\dds_test\topdesign.ngm (188885, 2011-03-09)
03-移相信号发生器（2003年C题）\dds_test\topdesign.ngr (30441, 2011-03-09)
03-移相信号发生器（2003年C题）\dds_test\topdesign.pad (8920, 2011-03-09)
03-移相信号发生器（2003年C题）\dds_test\topdesign.pad_txt (39890, 2011-03-09)
03-移相信号发生器（2003年C题）\dds_test\topdesign.par (3529, 2011-03-09)
03-移相信号发生器（2003年C题）\dds_test\topdesign.pcf (1688, 2011-03-09)
03-移相信号发生器（2003年C题）\dds_test\topdesign.placed_ncd_tracker (0, 2011-03-09)
03-移相信号发生器（2003年C题）\dds_test\topdesign.prj (54, 2011-03-09)
03-移相信号发生器（2003年C题）\dds_test\topdesign.routed_ncd_tracker (0, 2011-03-09)
03-移相信号发生器（2003年C题）\dds_test\topdesign.stx (0, 2011-03-09)
... ...
The following files were generated for in directory
F:\taojian\yixiangqi_demo3\dds_test:
dds_sin_TRIG_ROM.mif:
Memory Initialization File which is automatically generated by the
CORE Generator System for some modules when a simulation flow is
specified. A MIF data file is used to support HDL functional
simulation of modules which use arrays of values.
dds_sin.edn:
Electronic Data Netlist (EDN) file containing the information
required to implement the module in a Xilinx (R) FPGA.
dds_sin.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
dds_sin.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
dds_sin.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
dds_sin.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
dds_sin.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
dds_sin.sym:
Please see the core data sheet.
dds_sin.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
dds_sin_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
dds_sin_readme.txt:
Text file indicating the files generated and how they are used.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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