05-NEC_2003_D

所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:408KB
下载次数:10
上传日期:2012-06-05 22:34:10
上 传 者Emily0626
说明:  简易逻辑分析仪(2003年D题),verilog源程序
(Simple logic analyzer (, 2003 D), Verilog source code)

文件列表:
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\automake.log (0, 2011-03-10)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\bitgen.ut (518, 2011-03-10)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\core.tpl (1827, 2011-03-08)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\dpram256x12.asy (761, 2011-03-08)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\dpram256x12.edn (83594, 2011-03-08)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\dpram256x12.ngo (33343, 2011-03-08)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\dpram256x12.sym (1132, 2011-03-08)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\dpram256x12.v (4908, 2011-03-08)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\dpram256x12.veo (3041, 2011-03-08)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\dpram256x12.vhd (5162, 2011-03-08)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\dpram256x12.vho (3778, 2011-03-08)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\dpram256x12.xco (1915, 2011-03-08)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\dpram256x12_flist.txt (199, 2011-03-08)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\shibo.bgn (5072, 2011-03-10)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\shibo.bit (167051, 2011-03-10)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\shibo.bld (898, 2011-03-10)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\shibo.cmd_log (2558, 2011-03-10)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\shibo.drc (38, 2011-03-10)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\shibo.lso (6, 2011-03-10)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\shibo.mrp (26161, 2011-03-10)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\shibo.nc1 (37, 2011-03-10)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\shibo.ncd (68410, 2011-03-10)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\shibo.ngc (73266, 2011-03-10)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\shibo.ngd (154170, 2011-03-10)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\shibo.ngm (247443, 2011-03-10)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\shibo.ngr (48590, 2011-03-10)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\shibo.pad (9324, 2011-03-10)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\shibo.pad_txt (39882, 2011-03-10)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\shibo.par (3505, 2011-03-10)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\shibo.pcf (2304, 2011-03-10)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\shibo.placed_ncd_tracker (0, 2011-03-10)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\shibo.prj (58, 2011-03-10)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\shibo.routed_ncd_tracker (0, 2011-03-10)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\shibo.stx (0, 2011-03-10)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\shibo.syr (16734, 2011-03-10)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\shibo.twr (4027, 2011-03-10)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\shibo.twx (18822, 2011-03-10)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\shibo.ucf (1515, 2011-02-14)
05-简易逻辑分析仪(2003年D题)\luojiyi_demo\shibo.ucf.untf (0, 2011-03-10)
... ...

The following files were generated for in directory F:\taojian\shiboqi\shiboqi_demo: dpram256x12.edn: Electronic Data Netlist (EDN) file containing the information required to implement the module in a Xilinx (R) FPGA. dpram256x12.vhd: VHDL wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core. dpram256x12.vho: VHO template file containing code that can be used as a model for instantiating a CORE Generator module in a VHDL design. dpram256x12.v: Verilog wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core. dpram256x12.veo: VEO template file containing code that can be used as a model for instantiating a CORE Generator module in a Verilog design. dpram256x12.asy: Graphical symbol information file. Used by the ISE tools and some third party tools to create a symbol representing the core. dpram256x12.sym: Please see the core data sheet. dpram256x12.xco: CORE Generator input file containing the parameters used to regenerate a core. dpram256x12_flist.txt: Text file listing all of the output files produced when a customized core was generated in the CORE Generator. dpram256x12_readme.txt: Text file indicating the files generated and how they are used. Please see the Xilinx CORE Generator online help for further details on generated files and how to use them.

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