06-NEC_2005_A
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：707KB
下载次数：8
上传日期：2012-06-05 22:34:59
上 传 者：
Emily0626
说明： 06-正弦信号发生器（2005年A题），verilog源程序
(06- sinusoidal signal generator (2005 A question), Verilog source code)
文件列表:
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\automake.log (0, 2011-04-01)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\bitgen.ut (518, 2011-04-01)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\core.tpl (1358, 2011-03-07)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\dds_cos.asy (386, 2011-03-07)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\dds_cos.edn (62503, 2011-03-07)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\dds_cos.ngo (25948, 2011-03-07)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\dds_cos.sym (570, 2011-03-07)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\dds_cos.v (3827, 2011-03-07)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\dds_cos.veo (2965, 2011-03-07)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\dds_cos.vhd (3944, 2011-03-07)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\dds_cos.vho (3549, 2011-03-07)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\dds_cos.xco (1154, 2011-03-07)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\dds_cos_flist.txt (181, 2011-03-07)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\dds_cos_TRIG_ROM.mif (16384, 2011-03-07)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\Project.dhp (1066, 2011-03-07)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\sin.bgn (5064, 2011-04-01)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\sin.bit (167049, 2011-04-01)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\sin.bld (724, 2011-04-01)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\sin.cmd_log (3330, 2011-04-01)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\sin.dhp (1754, 2011-04-01)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\sin.drc (38, 2011-04-01)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\sin.ise (4531, 2011-04-01)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\sin.ise_ISE_Backup (4531, 2011-04-01)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\sin.lso (6, 2011-04-01)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\sin.mrp (12149, 2011-04-01)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\sin.nc1 (37, 2011-04-01)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\sin.ncd (144774, 2011-04-01)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\sin.ngc (138983, 2011-04-01)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\sin.ngd (269194, 2011-04-01)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\sin.ngm (468703, 2011-04-01)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\sin.ngr (136785, 2011-04-01)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\sin.pad (8802, 2011-04-01)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\sin.pad_txt (39878, 2011-04-01)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\sin.par (4002, 2011-04-01)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\sin.pcf (1543, 2011-04-01)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\sin.placed_ncd_tracker (0, 2011-04-01)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\sin.prj (48, 2011-04-01)
06-正弦信号发生器（2005年A题）\zhengxianbo_demo\sin.routed_ncd_tracker (0, 2011-04-01)
... ...
The following files were generated for in directory
F:\taojian\zhengxinbo_demo_new\sin:
dds_cos_TRIG_ROM.mif:
Memory Initialization File which is automatically generated by the
CORE Generator System for some modules when a simulation flow is
specified. A MIF data file is used to support HDL functional
simulation of modules which use arrays of values.
dds_cos.edn:
Electronic Data Netlist (EDN) file containing the information
required to implement the module in a Xilinx (R) FPGA.
dds_cos.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
dds_cos.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
dds_cos.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
dds_cos.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
dds_cos.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
dds_cos.sym:
Please see the core data sheet.
dds_cos.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
dds_cos_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
dds_cos_readme.txt:
Text file indicating the files generated and how they are used.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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