FdplllzipP
所属分类：VHDL/FPGA/Verilog
开发工具：Visual C++
文件大小：5KB
下载次数：9
上传日期：2012-06-10 17:55:19
上 传 者：
accompanys
说明： ＦＰＧＡ实现全数字锁相环，运用硬件描述评议议verilog HDL，顶层文件ＤＰＬＬ．Ｖ
(FPGA implementation of DPLL, the use of hardware description council meeting Verilog HDL top-level file DPLL is. V)
文件列表:
FdplllzipP\dpll\divfrequency32.v (398, 2008-03-21)
FdplllzipP\dpll\divfrequency32_tp.v (264, 2008-03-20)
FdplllzipP\dpll\divfrequency64.v (429, 2008-03-21)
FdplllzipP\dpll\divfrequency64_tp.v (266, 2008-03-20)
FdplllzipP\dpll\divfrequency8.v (364, 2008-03-21)
FdplllzipP\dpll\divfrequency8_tp.v (275, 2008-03-20)
FdplllzipP\dpll\dpll.v (1520, 2008-03-21)
FdplllzipP\dpll\dpll_tp.v (375, 2008-03-27)
FdplllzipP\dpll\maichongjiajian.v (3292, 2008-03-20)
FdplllzipP\dpll\maichongjiajian_tp.v (385, 2008-03-20)
FdplllzipP\dpll\moKcounter.v (2253, 2008-03-21)
FdplllzipP\dpll\moKcounter_tp.v (385, 2008-03-20)
FdplllzipP\dpll\xorphd.v (161, 2008-03-21)
FdplllzipP\dpll\xorphd_tp.v (249, 2008-03-21)
FdplllzipP\dpll (0, 2008-05-05)
FdplllzipP (0, 2012-03-12)
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