PipelineSim

所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:67KB
下载次数:12
上传日期:2012-06-24 22:19:14
上 传 者zz89724h
说明:  一个计算机原理课程设计的作业,5级流水线CPU,指令集到代码均为自己设计,有最终报告文档,组建说明,并行除法,16位字长,定长指令,Verilog源代码,顶层设计图。结构简单,冲突解决方式也很简单,代码量小。
(A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of parallel division, 16-bit word length, fixed-length instructions, Verilog source code, top level design. Simple structure, conflict resolution is also very simple, a small amount of code.)

文件列表:
PipelineSim\ALU.v (3205, 2009-06-06)
PipelineSim\decoder.v (6010, 2009-06-10)
PipelineSim\IF.v (796, 2009-06-10)
PipelineSim\MemInterface.v (2846, 2009-06-11)
PipelineSim\Pipeline.v (4004, 2009-06-11)
PipelineSim\PipelineSim.cr.mti (2483, 2009-06-15)
PipelineSim\PipelineSim.mpf (28629, 2009-06-15)
PipelineSim\RegisterFile.v (1224, 2009-06-11)
PipelineSim\Simulate.v (2209, 2009-06-11)
PipelineSim\transcript (1863, 2009-06-09)
PipelineSim\vsim.wlf (40960, 2009-06-11)
PipelineSim\WB.v (2733, 2009-06-11)
PipelineSim\work\@a@l@u\verilog.asm (24183, 2009-06-11)
PipelineSim\work\@a@l@u\_primary.dat (3452, 2009-06-11)
PipelineSim\work\@a@l@u\_primary.vhd (671, 2009-06-11)
PipelineSim\work\@inst@decoder\verilog.asm (25813, 2009-06-11)
PipelineSim\work\@inst@decoder\_primary.dat (4170, 2009-06-11)
PipelineSim\work\@inst@decoder\_primary.vhd (981, 2009-06-11)
PipelineSim\work\@inst@fetch\verilog.asm (4695, 2009-06-11)
PipelineSim\work\@inst@fetch\_primary.dat (556, 2009-06-11)
PipelineSim\work\@inst@fetch\_primary.vhd (475, 2009-06-11)
PipelineSim\work\@mem@interface\verilog.asm (12309, 2009-06-11)
PipelineSim\work\@mem@interface\_primary.dat (1732, 2009-06-11)
PipelineSim\work\@mem@interface\_primary.vhd (870, 2009-06-11)
PipelineSim\work\@pipeline\verilog.asm (11899, 2009-06-11)
PipelineSim\work\@pipeline\_primary.dat (3036, 2009-06-11)
PipelineSim\work\@pipeline\_primary.vhd (543, 2009-06-11)
PipelineSim\work\@register@file\verilog.asm (10137, 2009-06-11)
PipelineSim\work\@register@file\_primary.dat (967, 2009-06-11)
PipelineSim\work\@register@file\_primary.vhd (561, 2009-06-11)
PipelineSim\work\@simulate\verilog.asm (11707, 2009-06-11)
PipelineSim\work\@simulate\_primary.dat (1719, 2009-06-11)
PipelineSim\work\@simulate\_primary.vhd (76, 2009-06-11)
PipelineSim\work\@write@back\verilog.asm (14957, 2009-06-11)
PipelineSim\work\@write@back\_primary.dat (2162, 2009-06-11)
PipelineSim\work\@write@back\_primary.vhd (494, 2009-06-11)
PipelineSim\work\ALU.v (3205, 2009-06-06)
PipelineSim\work\decoder.v (6011, 2009-06-09)
PipelineSim\work\IF.v (796, 2009-06-08)
PipelineSim\work\MemInterface.v (2826, 2009-06-06)
... ...

近期下载者

相关文件


收藏者