vga
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：707KB
下载次数：34
上传日期：2012-07-10 15:40:47
上 传 者：
chenguang900402
说明： VGA显示的verilog整个代码。在xilinx spartan6板子上测试。
(VGA display the verilog source code. Test in on xilinx spartan6 board.)
文件列表:
vga\.compxlib.log (0, 2011-07-26)
vga\anyfp.bld (4332, 2011-07-30)
vga\anyfp.cmd_log (306, 2011-07-30)
vga\anyfp.lso (6, 2011-07-30)
vga\anyfp.ngc (4257, 2011-07-30)
vga\anyfp.ngr (5889, 2011-07-30)
vga\anyfp.prj (24, 2011-07-30)
vga\anyfp.stx (0, 2011-07-30)
vga\anyfp.syr (13483, 2011-07-30)
vga\anyfp.v (427, 2011-07-26)
vga\anyfp.xst (1100, 2011-07-30)
vga\anyfp_xst.xrpt (12028, 2011-07-30)
vga\fuse.log (1156, 2011-07-30)
vga\ipcore_dir\.lso (16, 2011-07-26)
vga\ipcore_dir\adder.asy (423, 2011-07-26)
vga\ipcore_dir\adder.gise (1446, 2011-07-30)
vga\ipcore_dir\adder.ncf (0, 2011-07-30)
vga\ipcore_dir\adder.ngc (14145, 2011-07-26)
vga\ipcore_dir\adder.sym (1274, 2011-07-26)
vga\ipcore_dir\adder.v (15930, 2011-07-26)
vga\ipcore_dir\adder.veo (3002, 2011-07-26)
vga\ipcore_dir\adder.vhd (4255, 2011-07-26)
vga\ipcore_dir\adder.vho (3429, 2011-07-26)
vga\ipcore_dir\adder.xco (1771, 2011-07-26)
vga\ipcore_dir\adder.xise (5008, 2011-07-26)
vga\ipcore_dir\adder_flist.txt (221, 2011-07-26)
vga\ipcore_dir\adder_xmdf.tcl (2968, 2011-07-26)
vga\ipcore_dir\_xmsgs\netgen.xmsgs (665, 2011-07-26)
vga\ipcore_dir\_xmsgs\ngcbuild.xmsgs (367, 2011-07-26)
vga\ipcore_dir\_xmsgs\pn_parser.xmsgs (912, 2011-07-30)
vga\ipcore_dir\_xmsgs\xst.xmsgs (14336, 2011-07-26)
vga\iseconfig\vga.projectmgr (10035, 2011-07-30)
vga\iseconfig\vga.xreport (20637, 2011-07-30)
vga\iseconfig\vga0.xreport (20682, 2011-07-30)
vga\isim\isim_usage_statistics.html (1665, 2011-07-30)
vga\isim\temp\anyfp.sdb (2487, 2011-07-30)
vga\isim\temp\glbl.sdb (4307, 2011-07-30)
vga\isim\temp\vga0.sdb (3919, 2011-07-30)
vga\isim\temp\vga0_tf.sdb (1586, 2011-07-30)
... ...
The following files were generated for 'adder' in directory
E:\a\vga\ipcore_dir\
adder.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
adder.gise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
adder.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
adder.sym:
Please see the core data sheet.
adder.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
adder.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
adder.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
adder.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
adder.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
adder.xise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
adder_readme.txt:
Text file indicating the files generated and how they are used.
adder_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
adder_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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