fir
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：982KB
下载次数：117
上传日期：2012-07-11 20:29:38
上 传 者：
huangyuanwang
说明： fir滤波器的几种结构virelog代码（串行，并行，DA结构以及多相抽取结构），程序包为ise工程
(fir filter several the structure virelog code (serial, parallel, DA structure and multiphase extraction structure), the program package for the ise project)
文件列表:
fir\firfilter\1.wcfg (5635, 2012-07-04)
fir\firfilter\2.wcfg (5897, 2012-07-03)
fir\firfilter\3.wcfg (6851, 2012-07-03)
fir\firfilter\4.wcfg (4721, 2012-07-05)
fir\firfilter\da_fir.cmd_log (114, 2012-07-06)
fir\firfilter\da_fir.lso (6, 2012-07-06)
fir\firfilter\da_fir.ngc (138104, 2012-07-06)
fir\firfilter\da_fir.ngr (124993, 2012-07-06)
fir\firfilter\da_fir.prj (52, 2012-07-06)
fir\firfilter\da_fir.stx (0, 2012-07-06)
fir\firfilter\da_fir.syr (27280, 2012-07-06)
fir\firfilter\da_fir.v (4999, 2012-07-05)
fir\firfilter\da_fir.xst (1103, 2012-07-06)
fir\firfilter\da_fir_envsettings.html (8780, 2012-07-11)
fir\firfilter\da_fir_summary.html (5186, 2012-07-11)
fir\firfilter\da_fir_tb.v (1517, 2012-07-06)
fir\firfilter\da_fir_tb_isim_beh.exe (82432, 2012-07-06)
fir\firfilter\da_fir_tb_stx_beh.prj (154, 2012-07-06)
fir\firfilter\da_fir_xst.xrpt (13144, 2012-07-06)
fir\firfilter\DA_table.lso (6, 2012-07-05)
fir\firfilter\DA_table.prj (27, 2012-07-05)
fir\firfilter\DA_table.stx (1682, 2012-07-05)
fir\firfilter\DA_table.v (1370, 2012-07-05)
fir\firfilter\DA_table.xst (1158, 2012-07-05)
fir\firfilter\fir.v (3413, 2012-07-04)
fir\firfilter\firfilter.gise (11952, 2012-07-11)
fir\firfilter\firfilter.xise (39254, 2012-07-08)
fir\firfilter\fir_2_chouqu.lso (6, 2012-07-06)
fir\firfilter\fir_2_chouqu.prj (31, 2012-07-06)
fir\firfilter\fir_2_chouqu.stx (1694, 2012-07-06)
fir\firfilter\fir_2_chouqu.v (1982, 2012-07-06)
fir\firfilter\fir_2_chouqu.xst (1166, 2012-07-06)
fir\firfilter\fir_2_chouqu_tb.v (1476, 2012-07-06)
fir\firfilter\fir_2_chouqu_tb_isim_beh.exe (82432, 2012-07-06)
fir\firfilter\fir_2_chouqu_tb_stx_beh.prj (134, 2012-07-06)
fir\firfilter\fuse.log (1510, 2012-07-08)
fir\firfilter\fuse.xmsgs (567, 2012-07-08)
fir\firfilter\fuseRelaunch.cmd (254, 2012-07-08)
fir\firfilter\ipcore_dir\coregen.cgp (237, 2012-07-03)
fir\firfilter\ipcore_dir\coregen.log (579, 2012-07-06)
... ...
The following files were generated for 'mult1' in directory
E:\ise\project\fir\firfilter\ipcore_dir\
Generate XCO file:
CORE Generator input file containing the parameters used to regenerate a
core.
* mult1.xco
Generate Implementation Netlist:
Binary Xilinx implementation netlist files containing the information
required to implement the module in a Xilinx (R) FPGA.
* mult1.ngc
Generate Obfuscated Netlist:
Translate the encrypted netlist into an obfuscated netlist.
* mult1.ngc
Generate Instantiation Templates:
Template files containing code that can be used as a model for instantiating
a CORE Generator module in a VHDL design.
* mult1.veo
RTL Simulation Model Generator:
Please see the core data sheet.
* mult1.v
All Documents Generator:
Please see the core data sheet.
* mult1/doc/mult_gen_ds255.pdf
* mult1/doc/mult_gen_v11_2_vinfo.html
Deliver IP Symbol:
Graphical symbol information file. Used by the ISE tools and some third party
tools to create a symbol representing the core.
* mult1.asy
SYM file generator:
Generate a SYM file for compatibility with legacy flows
* mult1.sym
Generate XMDF file:
ISE Project Navigator interface file. ISE uses this file to determine how the
files output by CORE Generator for the core can be integrated into your ISE
project.
* mult1_xmdf.tcl
Generate ISE project file:
ISE Project Navigator support files. These are generated files and should not
be edited directly.
* mult1.gise
* mult1.xise
Deliver Readme:
Text file indicating the files generated and how they are used.
* mult1_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* mult1_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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