lms
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：2740KB
下载次数：281
上传日期：2012-07-11 20:49:06
上 传 者：
huangyuanwang
说明： 文件中为lms算法的ise工程，其中包含了lms算法的fpga实现的verilog程序以及testbench，很好的在FPGA上实现了lms算法，还有一些调试程序的总结
(Ise project file for lms algorithm, which contains the lms algorithm fpga verilog program to achieve and testbench good lms algorithm implemented on FPGA debugger summary)
文件列表:
lms\mylms\fuse.log (2376, 2012-07-11)
lms\mylms\fuse.xmsgs (1175, 2012-07-11)
lms\mylms\fuseRelaunch.cmd (252, 2012-07-11)
lms\mylms\ipcore_dir\coregen.cgp (237, 2012-07-10)
lms\mylms\ipcore_dir\coregen.log (664, 2012-07-11)
lms\mylms\ipcore_dir\create_mult.tcl (1247, 2012-07-09)
lms\mylms\ipcore_dir\create_multadd.tcl (1266, 2012-07-09)
lms\mylms\ipcore_dir\create_shift_reg.tcl (1286, 2012-07-09)
lms\mylms\ipcore_dir\edit_mult.tcl (1120, 2012-07-09)
lms\mylms\ipcore_dir\edit_multadd.tcl (1123, 2012-07-11)
lms\mylms\ipcore_dir\edit_shift_reg.tcl (1125, 2012-07-09)
lms\mylms\ipcore_dir\mult\doc\dsp48_macro_ds754.pdf (500330, 2012-07-08)
lms\mylms\ipcore_dir\mult\doc\mult_gen_ds255.pdf (302354, 2012-07-09)
lms\mylms\ipcore_dir\mult\doc\mult_gen_v11_2_vinfo.html (7746, 2012-07-09)
lms\mylms\ipcore_dir\mult\doc\xbip_dsp48_macro_v2_1_vinfo.html (6395, 2012-07-08)
lms\mylms\ipcore_dir\mult.asy (506, 2012-07-09)
lms\mylms\ipcore_dir\mult.gise (2587, 2012-07-11)
lms\mylms\ipcore_dir\mult.ncf (0, 2012-07-09)
lms\mylms\ipcore_dir\mult.ngc (23594, 2012-07-09)
lms\mylms\ipcore_dir\mult.sym (1486, 2012-07-09)
lms\mylms\ipcore_dir\mult.v (34600, 2012-07-09)
lms\mylms\ipcore_dir\mult.veo (3639, 2012-07-09)
lms\mylms\ipcore_dir\mult.xco (1903, 2012-07-09)
lms\mylms\ipcore_dir\mult.xise (4757, 2012-07-09)
lms\mylms\ipcore_dir\multadd\doc\dsp48_macro_ds754.pdf (500330, 2012-07-10)
lms\mylms\ipcore_dir\multadd\doc\xbip_dsp48_macro_v2_1_vinfo.html (6395, 2012-07-10)
lms\mylms\ipcore_dir\multadd.asy (683, 2012-07-10)
lms\mylms\ipcore_dir\multadd.gise (2600, 2012-07-11)
lms\mylms\ipcore_dir\multadd.ncf (0, 2012-07-09)
lms\mylms\ipcore_dir\multadd.ngc (57205, 2012-07-10)
lms\mylms\ipcore_dir\multadd.sym (1954, 2012-07-10)
lms\mylms\ipcore_dir\multadd.v (23543, 2012-07-10)
lms\mylms\ipcore_dir\multadd.veo (4478, 2012-07-10)
lms\mylms\ipcore_dir\multadd.xco (3301, 2012-07-10)
lms\mylms\ipcore_dir\multadd.xise (4775, 2012-07-11)
lms\mylms\ipcore_dir\multadd_flist.txt (304, 2012-07-10)
lms\mylms\ipcore_dir\multadd_xmdf.tcl (3039, 2012-07-10)
lms\mylms\ipcore_dir\mult_flist.txt (252, 2012-07-09)
... ...
The following files were generated for 'mult' in directory
E:\ise\project\lms\mylms\ipcore_dir\
Generate XCO file:
CORE Generator input file containing the parameters used to regenerate a
core.
* mult.xco
Generate Implementation Netlist:
Binary Xilinx implementation netlist files containing the information
required to implement the module in a Xilinx (R) FPGA.
* mult.ngc
Generate Obfuscated Netlist:
Translate the encrypted netlist into an obfuscated netlist.
* mult.ngc
Generate Instantiation Templates:
Template files containing code that can be used as a model for instantiating
a CORE Generator module in a VHDL design.
* mult.veo
RTL Simulation Model Generator:
Please see the core data sheet.
* mult.v
All Documents Generator:
Please see the core data sheet.
* mult/doc/mult_gen_ds255.pdf
* mult/doc/mult_gen_v11_2_vinfo.html
Deliver IP Symbol:
Graphical symbol information file. Used by the ISE tools and some third party
tools to create a symbol representing the core.
* mult.asy
SYM file generator:
Generate a SYM file for compatibility with legacy flows
* mult.sym
Generate XMDF file:
ISE Project Navigator interface file. ISE uses this file to determine how the
files output by CORE Generator for the core can be integrated into your ISE
project.
* mult_xmdf.tcl
Generate ISE project file:
ISE Project Navigator support files. These are generated files and should not
be edited directly.
* _xmsgs/pn_parser.xmsgs
* mult.gise
* mult.xise
Deliver Readme:
Text file indicating the files generated and how they are used.
* mult_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* mult_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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