sdram_control
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：2720KB
下载次数：5
上传日期：2012-07-17 17:28:54
上 传 者：
xiaojuan19881112
说明： 该代码主要实现了对静态sram的控制，分为三个模块，控制部分，数据产生路径部分，实现了对sram的写入与读出操作。
(The code is mainly to achieve the static SRAM control, is divided into three modules, control, data generating portion of the path, SRAM implementation of write and read operations.)
文件列表:
sdram_control\doc\read_me.doc (24576, 2005-11-22)
sdram_control\doc\SDRAM.doc (417280, 2005-12-15)
sdram_control\doc\sdr_sdram.pdf (917283, 2002-09-02)
sdram_control\sim\altera_mf.qpf (1263, 2012-07-12)
sdram_control\sim\altera_mf.qsf (2392, 2012-07-12)
sdram_control\sim\altera_mf.qws (533, 2012-07-12)
sdram_control\sim\altera_mf.v (1139393, 2004-11-28)
sdram_control\sim\Command.v (17532, 2005-06-18)
sdram_control\sim\control_interface.v (8494, 2004-11-28)
sdram_control\sim\db\altera_mf.db_info (137, 2012-07-12)
sdram_control\sim\db\altera_mf.eco.cdb (161, 2012-07-12)
sdram_control\sim\db\altera_mf.sld_design_entry.sci (154, 2012-07-12)
sdram_control\sim\mt48lc2m32b2.v (50092, 2004-09-03)
sdram_control\sim\Params.v (935, 2005-06-14)
sdram_control\sim\sdram_test.cr.mti (4318, 2005-12-17)
sdram_control\sim\sdram_test.mpf (23380, 2005-12-17)
sdram_control\sim\sdram_test.wlf (57344, 2005-11-22)
sdram_control\sim\sdram_test_tb.v (7397, 2005-12-17)
sdram_control\sim\transcript (4605, 2005-12-15)
sdram_control\sim\vsim.wlf (57344, 2005-12-17)
sdram_control\sim\wave.do (2616, 2005-12-17)
sdram_control\sim\work\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\verilog.asm (28793, 2005-12-17)
sdram_control\sim\work\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\_primary.dat (2947, 2005-12-17)
sdram_control\sim\work\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\_primary.vhd (104, 2005-12-17)
sdram_control\sim\work\@m@f_pll_reg\verilog.asm (4304, 2005-12-17)
sdram_control\sim\work\@m@f_pll_reg\_primary.dat (478, 2005-12-17)
sdram_control\sim\work\@m@f_pll_reg\_primary.vhd (354, 2005-12-17)
sdram_control\sim\work\@m@f_ram7x20_syn\verilog.asm (26147, 2005-12-17)
sdram_control\sim\work\@m@f_ram7x20_syn\_primary.dat (2141, 2005-12-17)
sdram_control\sim\work\@m@f_ram7x20_syn\_primary.vhd (586, 2005-12-17)
sdram_control\sim\work\@m@f_stratixii_pll\verilog.asm (596560, 2005-12-17)
sdram_control\sim\work\@m@f_stratixii_pll\_primary.dat (52333, 2005-12-17)
sdram_control\sim\work\@m@f_stratixii_pll\_primary.vhd (6750, 2005-12-17)
sdram_control\sim\work\@m@f_stratix_pll\verilog.asm (753435, 2005-12-17)
sdram_control\sim\work\@m@f_stratix_pll\_primary.dat (72503, 2005-12-17)
sdram_control\sim\work\@m@f_stratix_pll\_primary.vhd (8453, 2005-12-17)
sdram_control\sim\work\alt3pram\verilog.asm (147437, 2005-12-17)
sdram_control\sim\work\alt3pram\_primary.dat (10137, 2005-12-17)
sdram_control\sim\work\alt3pram\_primary.vhd (1938, 2005-12-17)
sdram_control\sim\work\altaccumulate\verilog.asm (53145, 2005-12-17)
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