video_stream_scaler
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：5511KB
下载次数：516
上传日期：2012-07-21 01:16:48
上 传 者：
gtic_chenj
说明： Verilog HDL实现双线性插值视频实时缩放，源码及说明文档
(Verilog HDL bilinear interpolation real-time zoom, video source and documentation)
文件列表:
video_stream_scaler\trunk\doc\src\Block Diagram.vsd (58368, 2011-02-25)
video_stream_scaler\trunk\doc\src\Video Stream Scaler Specifications.doc (284672, 2011-02-25)
video_stream_scaler\trunk\doc\Video Stream Scaler Specifications.pdf (239471, 2011-02-25)
video_stream_scaler\trunk\rtl\verilog\scaler.v (26640, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\scaler.cr.mti (2, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\scaler.mpf (69320, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\scaler.v (26640, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\scaler_tb.v (11186, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\src\input.tif (3964132, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\src\input1280x1024boxdiag.bmp (163902, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\src\input1280x1024boxdiagRGB.raw (3932160, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\src\input1280x1024RGB.raw (3932160, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\src\input640x512boxdiag.bmp (328758, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\src\input640x512boxdiagRGB.raw (983040, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\src\input640x512RGB.raw (983040, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\src\input640x512_21extraRGB.raw (983103, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\vsim.wlf (16384, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\work\ram@dual@port\verilog.asm (12904, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\work\ram@dual@port\verilog.rw (2510, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\work\ram@dual@port\_primary.dat (654, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\work\ram@dual@port\_primary.dbs (1755, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\work\ram@dual@port\_primary.vhd (626, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\work\ram@fifo\verilog.asm (50576, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\work\ram@fifo\verilog.rw (6800, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\work\ram@fifo\_primary.dat (2656, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\work\ram@fifo\_primary.dbs (7124, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\work\ram@fifo\_primary.vhd (930, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\work\scaler@test\verilog.asm (40088, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\work\scaler@test\verilog.rw (9137, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\work\scaler@test\_primary.dat (2942, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\work\scaler@test\_primary.dbs (6709, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\work\scaler@test\_primary.vhd (991, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\work\scaler@testbench\verilog.asm (34320, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\work\scaler@testbench\verilog.rw (14655, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\work\scaler@testbench\_primary.dat (4203, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\work\scaler@testbench\_primary.dbs (3428, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\work\scaler@testbench\_primary.vhd (149, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\work\stream@scaler\verilog.asm (136256, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\work\stream@scaler\verilog.rw (17332, 2011-02-25)
video_stream_scaler\trunk\sim\rtl_sim\work\stream@scaler\_primary.dat (10192, 2011-02-25)
... ...
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