EEthhernet_vet
所属分类:VHDL/FPGA/Verilog
开发工具:Visual C++
文件大小:886KB
下载次数:42
上传日期:2012-07-22 22:00:54
上 传 者:
zheextent
说明: Ethernet(以太网)verilog ip core用veriloggHDL语言写的以太网软核,对学习verilog语言与以太网有非常大帮助。
(Ethernet (Ethernet) Verilog the ip core with veriloggHDL language Ethernet soft-core, there is a very big help to learn verilog language and Ethernet.)
文件列表:
EEthhernet_vet\ethernet\bench\CVS\Entries (3, 2005-07-19)
EEthhernet_vet\ethernet\bench\CVS\Entries.Log (17, 2005-07-19)
EEthhernet_vet\ethernet\bench\CVS\Repository (16, 2005-07-19)
EEthhernet_vet\ethernet\bench\CVS\Root (57, 2005-07-19)
EEthhernet_vet\ethernet\bench\CVS\Template (0, 2005-07-19)
EEthhernet_vet\ethernet\bench\verilog\CVS\Entries (687, 2005-07-19)
EEthhernet_vet\ethernet\bench\verilog\CVS\Repository (24, 2005-07-19)
EEthhernet_vet\ethernet\bench\verilog\CVS\Root (57, 2005-07-19)
EEthhernet_vet\ethernet\bench\verilog\CVS\Template (0, 2005-07-19)
EEthhernet_vet\ethernet\bench\verilog\eth_host.v (4895, 2002-07-19)
EEthhernet_vet\ethernet\bench\verilog\eth_memory.v (6115, 2002-07-19)
EEthhernet_vet\ethernet\bench\verilog\eth_phy.v (42953, 2003-01-23)
EEthhernet_vet\ethernet\bench\verilog\eth_phy_defines.v (4548, 2002-09-13)
EEthhernet_vet\ethernet\bench\verilog\tb_cop.v (14116, 2002-07-19)
EEthhernet_vet\ethernet\bench\verilog\tb_ethernet.v (1000395, 2005-03-22)
EEthhernet_vet\ethernet\bench\verilog\tb_ethernet_with_cop.v (20368, 2003-10-17)
EEthhernet_vet\ethernet\bench\verilog\tb_eth_defines.v (10956, 2003-06-13)
EEthhernet_vet\ethernet\bench\verilog\tb_eth_top.v (53084, 2002-09-06)
EEthhernet_vet\ethernet\bench\verilog\wb_bus_mon.v (19361, 2003-12-05)
EEthhernet_vet\ethernet\bench\verilog\wb_master32.v (13921, 2002-09-13)
EEthhernet_vet\ethernet\bench\verilog\wb_master_behavioral.v (24117, 2002-09-13)
EEthhernet_vet\ethernet\bench\verilog\wb_model_defines.v (7479, 2003-12-05)
EEthhernet_vet\ethernet\bench\verilog\wb_slave_behavioral.v (12720, 2004-03-26)
EEthhernet_vet\ethernet\CVS\Entries (47, 2005-07-19)
EEthhernet_vet\ethernet\CVS\Entries.Log (54, 2005-07-19)
EEthhernet_vet\ethernet\CVS\Repository (10, 2005-07-19)
EEthhernet_vet\ethernet\CVS\Root (57, 2005-07-19)
EEthhernet_vet\ethernet\CVS\Template (0, 2005-07-19)
EEthhernet_vet\ethernet\doc\CVS\Entries (252, 2005-07-19)
EEthhernet_vet\ethernet\doc\CVS\Entries.Log (13, 2005-07-19)
EEthhernet_vet\ethernet\doc\CVS\Repository (14, 2005-07-19)
EEthhernet_vet\ethernet\doc\CVS\Root (57, 2005-07-19)
EEthhernet_vet\ethernet\doc\CVS\Template (0, 2005-07-19)
EEthhernet_vet\ethernet\doc\ethernet_datasheet_OC_head.pdf (20169, 2002-09-21)
EEthhernet_vet\ethernet\doc\ethernet_product_brief_OC_head.pdf (19905, 2002-09-21)
EEthhernet_vet\ethernet\doc\eth_design_document.pdf (162784, 2002-10-30)
EEthhernet_vet\ethernet\doc\eth_speci.pdf (254051, 2002-11-28)
EEthhernet_vet\ethernet\doc\src\CVS\Entries (252, 2005-07-19)
EEthhernet_vet\ethernet\doc\src\CVS\Repository (18, 2005-07-19)
EEthhernet_vet\ethernet\doc\src\CVS\Root (57, 2005-07-19)
... ...
//////////////////////////////////////////////////////////////////////
//// ////
//// README.txt ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: README.txt,v $
// Revision 1.1 2002/09/18 16:50:08 mohor
// Several information added to the file.
//
//
//
//
RUNNING the simulation/Testbench in ModelSIM:
Open ModelSIM project: ethernet/sim/rtl_sim/modelsim_sim/bin/ethernet.mpf
Run the macro do.do (write "do do.do" in the command window).
Simulation will be automatically started. Logs are stored in the /log
directory. tb_ethernet test is performed.
RUNNING the simulation/Testbench in Ncsim:
Go to the ethernet\sim\rtl_sim\ncsim_sim\run directory. Run the
run_eth_sim_regr.scr script. Simulation is automatically started. Logs are
stored in the /log directory. Before running the script for another time,
run the clean script that deletes files from previous runs. tb_ethernet test
is performed.
Why are eth_cop.v, eth_host.v, eth_memory, tb_cop.v and tb_ethernet_with_cop.v
files used for?
Although the testbench does not include the traffic coprocessor, the
coprocessor is part of the ethernet environment. eth_cop multiplexes
two wishbone interface between 4 modules:
- First wishbone master interface is connected to the HOST (eth_host)
- Second wishbone master interface is connected to the Ethernet Core (for
accessing data in the memory (eth_memory)).
- First wishbone slave interface is connected to the Ethernet Core (for
accessing registers and buffer descriptors).
- Second wishbone slave interface is connected to the memory (eth_memory)
so host can write data to the memory (or read data from the memory.
tb_cop.c is a testbench just for the traffic coprocessor (eth_cop).
tb_ethernet_with_cop.v is a simple testbench where all above mentioned
modules are connected into a single environment. Few packets are transmitted
and received. The "main" testbench is tb_ethernet.v file. It performs several
tests (eth_cop is not part of the simulation environment).
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