Vfirr_using__e
所属分类：VHDL/FPGA/Verilog
开发工具：Visual C++
文件大小：24KB
下载次数：3
上传日期：2012-07-26 16:26:51
上 传 者：
decisivess
说明： 一种基于verilog的fiir滤波，并带matlab仿真
(Based verilog fiir filter with matlab simulation)
文件列表:
Vfirr_using__e\fir_using_FPGA\adder.v (4308, 2002-07-10)
Vfirr_using__e\fir_using_FPGA\basic_fir.m (3931, 2002-04-09)
Vfirr_using__e\fir_using_FPGA\Basic_FIR.v (1501, 2002-04-05)
Vfirr_using__e\fir_using_FPGA\coeff_0_7.mif (1626, 2002-04-05)
Vfirr_using__e\fir_using_FPGA\coeff_1_6.mif (1625, 2002-04-05)
Vfirr_using__e\fir_using_FPGA\coeff_2_5.mif (1625, 2002-04-05)
Vfirr_using__e\fir_using_FPGA\coeff_3_4.mif (1626, 2002-04-05)
Vfirr_using__e\fir_using_FPGA\coeff_rom_0_7.v (4762, 2002-04-05)
Vfirr_using__e\fir_using_FPGA\coeff_rom_1_6.v (4762, 2002-04-05)
Vfirr_using__e\fir_using_FPGA\coeff_rom_2_5.v (4762, 2002-04-05)
Vfirr_using__e\fir_using_FPGA\coeff_rom_3_4.v (4762, 2002-04-05)
Vfirr_using__e\fir_using_FPGA\db\fir.db_info (136, 2007-07-31)
Vfirr_using__e\fir_using_FPGA\db\fir.eco.cdb (141, 2007-07-31)
Vfirr_using__e\fir_using_FPGA\db\fir.sld_design_entry.sci (134, 2007-07-31)
Vfirr_using__e\fir_using_FPGA\fir.qpf (898, 2007-07-31)
Vfirr_using__e\fir_using_FPGA\fir.qsf (1946, 2007-07-31)
Vfirr_using__e\fir_using_FPGA\fir.qws (1577, 2007-07-31)
Vfirr_using__e\fir_using_FPGA\impulse.vwf (27659, 2002-04-09)
Vfirr_using__e\fir_using_FPGA\mult_add.v (14300, 2002-04-05)
Vfirr_using__e\fir_using_FPGA\random.vwf (39313, 2002-04-09)
Vfirr_using__e\fir_using_FPGA\step.vwf (27642, 2002-04-09)
Vfirr_using__e\fir_using_FPGA\db (0, 2008-06-24)
Vfirr_using__e\fir_using_FPGA (0, 2008-06-24)
Vfirr_using__e (0, 2012-03-18)
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