nm49a_nand_moa
所属分类:VHDL/FPGA/Verilog
开发工具:Visual C++
文件大小:45KB
下载次数:12
上传日期:2012-08-06 06:36:44
上 传 者:
sanctionss
说明: nand flash 仿真模型,,支持ONFI 2.0
(nand flash simulation model to support the ONFI 2.0)
文件列表:
nm49a_nand_moa\nand_die_model.v (178838, 2008-10-22)
nm49a_nand_moa\nand_model.v (8179, 2008-10-22)
nm49a_nand_moa\nand_parameters.vh (17073, 2008-09-10)
nm49a_nand_moa\subtest.vh (915, 2008-06-19)
nm49a_nand_moa\tb.do (2095, 2008-06-19)
nm49a_nand_moa\tb.v (54037, 2008-10-22)
nm49a_nand_moa (0, 2012-03-18)
Disclaimer of Warranty:
-----------------------
This software code and all associated documentation, comments
or other information (collectively "Software") is provided
"AS IS" without warranty of any kind. MICRON TECHNOLOGY, INC.
("MTI") EXPRESSLY DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED,
INCLUDING BUT NOT LIMITED TO, NONINFRINGEMENT OF THIRD PARTY
RIGHTS, AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS
FOR ANY PARTICULAR PURPOSE. MTI DOES NOT WARRANT THAT THE
SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE OPERATION OF
THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. FURTHERMORE,
MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR THE
RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT
OF USE OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO
EVENT SHALL MTI, ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE
LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR
SPECIAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS
OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION)
ARISING OUT OF YOUR USE OF OR INABILITY TO USE THE SOFTWARE,
EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Because some jurisdictions prohibit the exclusion or limitation
of liability for consequential or incidental damages, the above
limitation may not apply to you.
Copyright 2008 Micron Technology, Inc. All rights reserved.
Getting Started:
----------------
Unzip the included files to a folder.
Compile nand_model.v, nand_die_model.v, and tb.v using a verilog simulator.
Simulate the top level test bench tb.
Or, if you are using the ModelSim simulator, type "do tb.do" at the prompt.
File Descriptions:
------------------
nand_model.v -structural wrapper for nand_die_model
nand_die_model.v -nand model of a single die
nand_parameters.vh -file that contains all parameters used by the model
readme.txt -this file
tb.v -nand model test bench
tb.do -compiles and runs the nand_model and test bench
Defining the Operating Voltage:
-------------------------------
The verilog compiler directive "`define" may be used to choose between
multiple operating voltages supported by the nand model. Valid
operating voltages include V18, and V33, and are listed in the
nand_parameters.vh file. The operating voltage is used to select the
timings associated with the nand model. The following are examples of
defining the operating voltage.
simulator command line
--------- ------------
ModelSim vlog +define+V33 nand_die_model.v
NC-Verilog ncverilog +v2k +define+V33 nand_die_model.v
VCS vcs +v2k +define+V33 nand_die_model.v
Defining the Width:
--------------------------
The verilog compiler directive "`define" may be used to choose between
multiple widths supported by the nand model. Valid widths include x8,
and x16, and are listed in the nand_parameters.vh file. The width is
used to select the amount of memory and the port sizes of the nand
model. The following are examples of defining the width.
simulator command line
--------- ------------
ModelSim vlog +define+x8 nand_die_model.v
NC-Verilog ncverilog +v2k +define+x8 nand_die_model.v
VCS vcs +v2k +define+x8 nand_die_model.v
Defining the Classification:
-------------------------
The verilog compiler directive "`define" may be used to choose between
multiple part classifications supported by the nand model. Allowable
classifications are listed in the nand_parameters.vh file and begin with the
letter "A". The classification is used to set the NUM_DIE, NUM_CE, and NUM_RB parameters in
nand_die_model. The
following are examples of defining the classification.
simulator command line
--------- ------------
ModelSim vlog +define+CLASSD nand_die_model.v
NC-Verilog ncverilog +v2k +define+CLASSD nand_die_model.v
VCS vcs +v2k +define+CLASSD nand_die_model.v
All combinations of classification are considered
valid by the nand model even though a Micron part may not exist for
every combination.
Allocating Memory:
------------------
An associative array has been implemented to reduce the amount of
static memory allocated by the nand model. The size of each entry in
the associative array is determided by the width (x8 or x16). The
number of entries in the array is controlled by the NUM_ROW parameter,
and is equal to NUM_ROW*NUM_COL. For example, if the NUM_ROW parameter
is equal to 10, the associative array will be large enough to store
10*NUM_COL writes to unique addresses. The following are examples of
setting the NUM_ROW parameter to 8.
simulator command line
--------- ------------
ModelSim vsim -GNUM_ROW=8 nand_model
NC-Verilog ncverilog +v2k +defparam+nand_die_model.NUM_ROW=8 nand_die_model.v
VCS vcs +v2k -pvalue+NUM_ROW=8 nand_die_model.v
It is possible to allocate memory for every address supported by the
nand model by using the verilog compiler directive "`define FullMem".
This procedure will improve simulation performance at the expense of
system memory. The following are examples of allocating memory for
every address.
Simulator command line
--------- ------------
ModelSim vlog +define+FullMem nand_die_model.v
NC-Verilog ncverilog +v2k +define+FullMem nand_die_model.v
VCS vcs +v2k +define+FullMem nand_die_model.v
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