Xedk_for_busyI
所属分类：VHDL/FPGA/Verilog
开发工具：Visual C++
文件大小：2190KB
下载次数：6
上传日期：2012-08-14 23:47:09
上 传 者：
wraps
说明： XILINX 出品 EDK快速学习资料。 EDK在 Xilinx FPGA上构架一个CPU软核， 以提高整个系统的灵活性，和可扩展性。
(XILINX produced the EDK rapid learning materials. EDK Xilinx FPGA architecture of a CPU soft core in order to improve overall system flexibility, and scalability.)
文件列表:
Xedk_for_busyI\EDK_for_Busy_People\EDK_overview.ppt (2322432, 2003-01-29)
Xedk_for_busyI\EDK_for_Busy_People\EDK_Overview_lab1.doc (555008, 2003-01-29)
Xedk_for_busyI\EDK_for_Busy_People\EDK_Overview_lab2.doc (1203712, 2003-01-29)
Xedk_for_busyI\EDK_for_Busy_People\EDK_Overview_lab3.doc (82432, 2003-01-29)
Xedk_for_busyI\EDK_for_Busy_People\EDK_Overview_lab4.doc (334336, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\EDK_Overview_lab5.doc (54272, 2003-01-29)
Xedk_for_busyI\EDK_for_Busy_People\integrate_my_ip_w_platgen.doc (53248, 2003-01-29)
Xedk_for_busyI\EDK_for_Busy_People\lab1\code\linker_script (1474, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab1\code\system.c (260, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab1\code\timer_interrupt.c (4231, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab1\data\system.ucf (2513, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab1\etc\bitgen.opt (941, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab1\etc\bitgen.ut (343, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab1\etc\download.cmd (271, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab1\etc\fast_runtime.opt (2848, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab1\etc\xc18v04_vq44.bsd (4669, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab1\sim.do (1655, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab1\system.mhs (4622, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab1\system.mhs.solution (4473, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab1\system.mss.solution (1239, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab1\system.xmp.solution (516, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab2\code\hello.c (260, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab2\code\linker_script (1474, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab2\code\timer_interrupt.c (3245, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab2\data\system.ucf (2511, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab2\etc\bitgen.opt (941, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab2\etc\bitgen.ut (343, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab2\etc\download.cmd (271, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab2\etc\fast_runtime.opt (2848, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab2\etc\lab2_golden.cmd (277, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab2\etc\xc18v04_vq44.bsd (4669, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab2\lab2_golden\download.bit (375883, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab2\myip\bram_block_v1_00_a\hdl\vhdl\bram1_elaborate.vhd (7432, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab2\myip\bram_block_v1_00_a\hdl\vhdl\bram2_elaborate.vhd (7432, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab2\sim.do (1655, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab2\system.mhs (4473, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab2\system.mss (946, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab2\system.mvs (125, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab2\system.xmp (479, 2003-01-22)
Xedk_for_busyI\EDK_for_Busy_People\lab3\code\linker_script (1474, 2003-01-22)
... ...
Lab 5: Design the system as a submodule
---------------------------------------
This design describes how to design a PowerPC sub-system
using XPS for another design
System Description
------------------
This system contains a simple PowerPC system. A GPIO and a BRAM is
connected to the OPB Bus and the program makes the LED blinking.
There is a top level design in system_stub.vhd, which is a
place holder generated by XPS if the project is setup as a
sub module. Users can add a DCM module in this level.
Refer to < your path of the lab>/mymisc for an example.
The system hierarchy looks like this:
system_stub_edit.vhd (managed by Project Navigator)
|
+ dcm_ip.vhd
|
+ system.vhd (managed by Platform Studio, defined by system.mhs)
|
+ ...
|
+ ...
Setup
-----
Set up board connections - JTAG cable from host computer to the board.
Building the sub-system in XPS
------------------------------
1. Start XPS GUI, open the project system.xmp
2. Options -> Project Options -> Hierarchy and Flow
- Is submodule and the top instance name is 'system_i1'.
(Since we using VHDL the case of the name is very important)
- Netlist Generation: choose 'Flat'
Synthesis tool choose 'ISE XST'
- Using ProjNav and the NPL file is projnav/system_stub_edit.npl
3. Now generate the netlist
'Tools' -> 'Generate Netlist'
4. Now export it to ProjNav:
'Tools' -> 'Export to ProjNav'
Complete the hw system in ProjNav
------------------------------
5. Open ISE Project Navigator
6. Open the project under /projnav/system_stub_edit.npl
7. Remove system_stub.vhd (we'll replace with the pre-made one)
8. Now add top level and misc files:
Project -> Add Sources ->
Select both /mymisc/system_stub_edit.vhd, dcm_ip.vhd
When ProjNav ask what kind of VHDL there are, answer with VHDL Module.
9. Now add the BMM file
Project -> Add Sources ->
/implementation/system_stub.bmm
Associate it with the system_stub_edit module
10. Now add the UCF file
Project -> Add Sources ->
/data/system_stub.ucf
Associate it with the system_stub_edit module
11. Now generate the bit file by running 'Generate Programming File'
Compile sw, download via XPS
------------------------------
12. Go back to XPS and import from ProjNav
'Tools' -> Import from ProjNav
Enter bit file : projnav/system_stub_edit.bit
Enter bmm file : implementation/system_stub_bd.bmm
14. Click on download button or 'Tools' -> 'Download'
It will run platgen, gcc, init_ram, impact to download the bit.
15. Now the leds on the board should blink
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