说明：  基于FPGA的单精度浮点数乘法器设计，本文设计了一个基于FPGA的单精度浮点数乘法器。乘法器为五级流水线结构。设计中采用了改进的带偏移量的冗余Booth3算法和跳跃式Wallace树型结构，减少了部分积的数目，缩短了部分积累加的耗时；提出了对尾数定点乘法运算中Wallace树产生的2个伪和采用部分相加的处理方式，有效地提高了的运算速度；并且加入了对特殊值的处理模块，完善了乘法器的功能。单精度浮点数乘法器在Altera DE2开发板上进行了验证，其在Cyclone II EP2C35F672C6器件上的最高工作频率达到212.13 MHz。
(FPGA-based single-precision floating-point multiplier design, design of an FPGA-based single-precision floating-point multiplier. Multipliers for the five pipeline structure. Design with improved offset the redundancy Booth3 algorithm and leapfrog Wallace tree structure to reduce the number of partial product, shorten the time-consuming part of the accumulated added on the Wallace tree in the fixed-point multiplication of mantissa two false and part of the additive approach, effectively improving the processing speed and joined the special value of the processing module, and improve the function of the multiplier. Single-precision floating-point multiplier on Altera DE2 development board for verification, its maximum operating frequency of the Cyclone II EP2C35F672C6 device to 212.13 MHz.)