viterbi_miniproj
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：535KB
下载次数：28
上传日期：2012-08-29 02:15:31
上 传 者：
kshuvadeep
说明： This project is about the implementation of soft viterbi decoder
文件列表:
viterbi_miniproj\acs_mod.vhd (1726, 2012-04-11)
viterbi_miniproj\bm_gen.vhd (1362, 2012-04-09)
viterbi_miniproj\complete_decoder.vhd (6105, 2012-04-25)
viterbi_miniproj\CONTROLLER.vhd (2446, 2012-04-13)
viterbi_miniproj\CONV_ENCODER.vhd (1657, 2012-04-13)
viterbi_miniproj\COUNTER.vhd (1535, 2012-04-08)
viterbi_miniproj\fpga_miniprjct.pdf (849893, 2012-04-28)
viterbi_miniproj\INPUT_GENERATOR.vhd (1646, 2012-04-26)
viterbi_miniproj\lifo.vhd (1550, 2012-04-13)
viterbi_miniproj\MEMORY.vhd (1519, 2012-04-07)
viterbi_miniproj\METRIC_UPDATE.vhd (5088, 2012-04-13)
viterbi_miniproj\PREDICTOR.vhd (2714, 2012-04-12)
viterbi_miniproj\RAM.vhd (1778, 2012-04-13)
viterbi_miniproj\random_channel.vhd (1670, 2012-04-15)
viterbi_miniproj\row_addr_generator.vhd (1282, 2012-04-08)
viterbi_miniproj (0, 2012-05-02)
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