DDDRR_SDRAM_cD
所属分类：VHDL/FPGA/Verilog
开发工具：Visual C++
文件大小：465KB
下载次数：8
上传日期：2012-08-29 23:00:50
上 传 者：
squeezes
说明： DDR SRAM控制器的verilog完整设设计文档（包含有完整的verilog源代码），
(DDR SRAM controller the verilog complete set design document (contains the complete source code verilog))
文件列表:
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top.txt (3025, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_addr_gen_0.txt (5114, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_backend_fifos_0.txt (4570, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_backend_rom_0.txt (5713, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_cmp_rd_data_0.txt (6558, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_controller_iobs_0.txt (3963, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_data_gen_16.txt (7581, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_data_path_0.txt (3881, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_data_path_iobs_0.txt (57608, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_data_tap_inc.txt (4020, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_data_write_0.txt (4833, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_ddr_controller_0.txt (54557, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_idelay_ctrl.txt (1358, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_infrastructure.txt (4202, 2007-09-29)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_infrastructure_iobs_0.txt (4596, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_iobs_0.txt (4714, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_main_0.txt (5122, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_parameters_0.txt (3773, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_pattern_compare8.txt (6498, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_RAM_D_0.txt (4598, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_rd_data_0.txt (19453, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_rd_data_fifo_0.txt (6672, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_rd_wr_addr_fifo_0.txt (4310, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_tap_ctrl_0.txt (16111, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_tap_logic_0.txt (5493, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_test_bench_0.txt (6736, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_top_0.txt (11119, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_user_interface_0.txt (3891, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_v4_dm_iob.txt (1576, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_v4_dqs_iob.txt (2697, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_v4_dq_iob.txt (2755, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top_wr_data_fifo_16.txt (2528, 2007-09-27)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\使用 Virtex-4 FPGA 器件实现DDR SDRAM控制器.pdf (639510, 2007-09-19)
DDDRR_SDRAM_cD\DDR SDRAM\使用说明请参看右侧注释====〉〉.txt (774, 2008-01-28)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM (0, 2008-03-16)
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM (0, 2007-10-28)
DDDRR_SDRAM_cD\DDR SDRAM (0, 2008-03-16)
DDDRR_SDRAM_cD (0, 2012-03-18)
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