文件列表:

examples\eetop.cn_CORDIC\cordic_parameteizaed.rar (1888, 2012-05-30)
examples\eetop.cn_CORDIC\cordic_pipelined.rar (1347, 2012-05-30)
examples\eetop.cn_CORDIC\利用CORDIC计算三教函数值.pdf (121838, 2012-05-30)
examples\xapp204_CAM Codes\Verilog\cam_generic_8s.v (20886, 2012-05-30)
examples\xapp204_CAM Codes\Verilog\cam_ramb4.v (3995, 2012-05-30)
examples\xapp204_CAM Codes\Verilog\CAM_Top.ucf (1262, 2012-05-30)
examples\xapp204_CAM Codes\Verilog\cam_top.v (4355, 2012-05-30)
examples\xapp204_CAM Codes\Verilog\Decode_1.v (1548, 2012-05-30)
examples\xapp204_CAM Codes\Verilog\Decode_2.v (1637, 2012-05-30)
examples\xapp204_CAM Codes\Verilog\Decode_3.v (1847, 2012-05-30)
examples\xapp204_CAM Codes\Verilog\Decode_4.v (2355, 2012-05-30)
examples\xapp204_CAM Codes\Verilog\encode_1_msb.v (3200, 2012-05-30)
examples\xapp204_CAM Codes\Verilog\encode_2_msb.v (4876, 2012-05-30)
examples\xapp204_CAM Codes\Verilog\encode_3_msb.v (6274, 2012-05-30)
examples\xapp204_CAM Codes\Verilog\encode_4_lsb.v (4293, 2012-05-30)
examples\xapp204_CAM Codes\Verilog\encode_4_msb.v (9112, 2012-05-30)
examples\xapp204_CAM Codes\Verilog\init_8_ram16x1s.v (4359, 2012-05-30)
examples\xapp204_CAM Codes\Verilog\init_ramb4_s1_s16.v (5327, 2012-05-30)
examples\xapp204_CAM Codes\Verilog\parameters.v (2308, 2012-05-30)
examples\xapp204_CAM Codes\Verilog\tb_cam_ramb4.v (12286, 2012-05-30)
examples\xapp204_CAM Codes\Verilog\transcript (390, 2012-05-30)
examples\xapp204_CAM Codes\Vhdl\CAM_generic_8s.vhd (13918, 2012-05-30)
examples\xapp204_CAM Codes\Vhdl\CAM_RAMB4.vhd (4384, 2012-05-30)
examples\xapp204_CAM Codes\Vhdl\CAM_Top.ucf (1299, 2012-05-30)
examples\xapp204_CAM Codes\Vhdl\CAM_top.vhd (4893, 2012-05-30)
examples\xapp204_CAM Codes\Vhdl\Decode_1.vhd (1875, 2012-05-30)
examples\xapp204_CAM Codes\Vhdl\Decode_2.vhd (1948, 2012-05-30)
examples\xapp204_CAM Codes\Vhdl\Decode_3.vhd (2125, 2012-05-30)
examples\xapp204_CAM Codes\Vhdl\Decode_4.vhd (2493, 2012-05-30)
examples\xapp204_CAM Codes\Vhdl\Encode_1_MSB.vhd (3346, 2012-05-30)
examples\xapp204_CAM Codes\Vhdl\Encode_2_MSB.vhd (4716, 2012-05-30)
examples\xapp204_CAM Codes\Vhdl\Encode_3_MSB.vhd (5838, 2012-05-30)
examples\xapp204_CAM Codes\Vhdl\Encode_4_LSB.vhd (3594, 2012-05-30)
examples\xapp204_CAM Codes\Vhdl\Encode_4_MSB.vhd (8350, 2012-05-30)
examples\xapp204_CAM Codes\Vhdl\Init_8_RAM16x1s.vhd (5332, 2012-05-30)
examples\xapp204_CAM Codes\Vhdl\Init_RAMB4_S1_S16.vhd (7289, 2012-05-30)
examples\xapp204_CAM Codes\Vhdl\TB_CAM_RAMB4.vhd (12214, 2012-05-30)
examples\xapp204_CAM Codes\Verilog (0, 2012-05-30)
... ...

README file: XAPP204 VHDL Reference Design ========================================== Date: Wed. September 28, 1999 Updates: 12/10/99 - JLB - Compilation with FPGA Express 3.3 and Alliance 2.1i SP3 Author: Jean-Louis Brelet / Xilinx File Name: ---------- xapp204_vhdl.zip, xapp204_vhdl.tar.Z Description: ------------ Contains the following files readme.txt : This file CAM_Top.ucf : Alliance Timing Constraints example for a CAM 32 words x 8 bits at 66 MHz CAM_top.vhd : Top VHDL wrapper file for testing CAM_generic_8s.vhd (Default CAM 32x8) CAM_generic_8s.vhd : Top level of the reference design (Parametrizable word width and depth) CAM_RAMB4.vhd : CAM module 16 x 8-bit Init_8_RAM16Xx1s.vhd : Basic Building block instantiating 8 RAM16x1s Init_RAMB4_S1_S16.vhd : Basic Building Block instantiating RAMB4 Encode_4_LSB.vhd : Encode a 16-bit binary address into 4 bits Encode_X_MSB.vhd : (available for 4, 3, 2 and 1 bit) Encode binary address into a X bits bus and add the LSB address Decode_X.vhd : (available for 4, 3, 2 and 1 bit) Decode X bits into a binary address TB_CAM_RAMB4.vhd : Test Bench for the module CAM_RAMB4.vhd Platform: --------- All Installation/Use: ----------------- Use 'unzip' on the .zip file and 'uncompress' followed by 'tar -xvf' on the .tar.Z file. Parametrizable VHDL code: ------------------------- Edit "CAM_top.vhd" Modify the "addr_width" to the required number of address lines (default = 5 address lines) Modify the "nb_cam_16words" to the equivalent number of CAM 16 words blocks (default = 2 blocks) Edit "CAM_generic_word.vhd" Remove the comments of the corresponding "Encode_X_MSB" and "Decode_X" instantiation By default the CAM 32 x 8 uses the Encode_1_MSB and Decode_1 instances. (Do NOT change or comment the Encode_4_LSB module, which is required by each basic CAM 16 word module) Functionnal Simulation: ----------------------- The design has been tested using Model Technology ModelSim EE 5.3a A testbench for the basic CAM_RAMB4.vhd is provided as example. Create a link to the UNISIM vhdl models library. (Please see documentation about functionnal simulation) Compile all the vhdl files included TB_CAM_RAMB4 (Test Bench) Load TB_CAM_RAMB4 and run the simulation. (Basic Write and Read operations) Synthesis: ---------- The design has been tested using Synopsys FPGA Express ver. 3.3 In the "Create Implementation" Template: Device = XCV100EPQ240 Speed grade = -6 Preserve Hierarchy = On Clock frequency = 66 MHz Export Netlist WITHOUT timing Implementation: --------------- The design has been tested using Xilinx Alliance ver. 2.1i SP3 targetting XCV100 or XCV100E (Please see the Alliance 2.1i documentation about how to use the tools) Use the "CAM_Top.ucf" file as timing constraints file Option: Constraint files with placement are available as example (Modify Init_8_RAM16x1s.vhd module to use RLOC) In the "Implementation / Optimize and Map" template: Select the Map option = Pack I/O registers into IOB for Inputs & Outputs Suggested High Place and Route effort MAP shows the following warning in the "map.mrp" report file: WARNING: Blockcheck: "Dangling BLKRAM output. Pin DOA0 of comp .../RAMB4 is nor connected" This warning can be ignored because the Block SelectRAM memories have no connection on the port A output. (Use as Write port only) Who to Contact if you have questions? http://www.xilinx.com/support/techsup/tappinfo.htm North American Support Hotline: 1-800-255-7778 or (408) 879-5199 Fax: (408) 879-4442 Email: hotline@xilinx.com United Kingdom Support Hotline: +44 870 7350 610 Fax: +44 870 7350 620 Email : ukhelp@xilinx.com France Support Hotline: +33 1 34 63 01 00 Fax: +33 1 34 63 09 59 Email : frhelp@xilinx.com Germany Support Hotline: +49 89 93088 130 Fax: +49 89 93088 188 Email : dlhelp@xilinx.com Japan Support Hotline: Local Distributor Fax: Local Distributor Email: jhotline@xilinx.com http://www.xilinx.com/support/techsup/japan.htm

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