文件列表:

cordic\cla\hdl\adder.v (2399, 2000-05-12)
cordic\cla\hdl\BitMux21.v (1747, 2000-05-12)
cordic\cla\hdl\BusMux21.v (1905, 2000-05-12)
cordic\cla\hdl\cla.v (2472, 2000-05-12)
cordic\cla\hdl\compl.v (3034, 2000-05-12)
cordic\cla\hdl\cordic.v (3615, 2000-05-12)
cordic\cla\hdl\header.v (1579, 2000-05-12)
cordic\cla\hdl\mem.pla (690, 2000-05-12)
cordic\cla\hdl\mem.v (3025, 2000-05-12)
cordic\cla\hdl\shifter.v (1687, 2000-05-12)
cordic\cla\hdl\sim.txt (89, 2000-05-12)
cordic\cla\hdl\stimulas.v (2338, 2000-05-12)
cordic\cla\script\syn.scr (1190, 2000-05-12)
cordic\cla.rca\hdl\adder.v (3413, 2000-05-12)
cordic\cla.rca\hdl\BitMux21.v (1747, 2000-05-12)
cordic\cla.rca\hdl\BusMux21.v (1905, 2000-05-12)
cordic\cla.rca\hdl\cla.v (2444, 2000-05-12)
cordic\cla.rca\hdl\compl.v (3037, 2000-05-12)
cordic\cla.rca\hdl\cordic.v (3605, 2000-05-12)
cordic\cla.rca\hdl\header.v (1626, 2000-05-12)
cordic\cla.rca\hdl\mem.pla (649, 2000-05-12)
cordic\cla.rca\hdl\mem.v (3026, 2000-05-12)
cordic\cla.rca\hdl\shifter.v (1686, 2000-05-12)
cordic\cla.rca\hdl\sim.txt (89, 2000-05-12)
cordic\cla.rca\hdl\stimulas.v (2339, 2000-05-12)
cordic\cla.rca\script\syn.scr (1190, 2000-05-12)
cordic\Makefile (915, 2000-05-12)
cordic\rca\hdl\adder.v (2399, 2000-05-12)
cordic\rca\hdl\BitMux21.v (1747, 2000-05-12)
cordic\rca\hdl\BusMux21.v (1905, 2000-05-12)
cordic\rca\hdl\compl.v (3034, 2000-05-12)
cordic\rca\hdl\cordic.v (3605, 2000-05-12)
cordic\rca\hdl\header.v (1579, 2000-05-12)
cordic\rca\hdl\mem.pla (649, 2000-05-12)
cordic\rca\hdl\mem.v (3025, 2000-05-12)
cordic\rca\hdl\rca.v (1694, 2000-05-12)
cordic\rca\hdl\shifter.v (1687, 2000-05-12)
cordic\rca\hdl\sim.txt (89, 2000-05-12)
cordic\rca\hdl\stimulas.v (2340, 2000-05-12)
cordic\rca\script\syn.scr (1191, 2000-05-12)
... ...

//---------------------------------------------------------------------------- //---------------------------------------------------------------------------- //-- The Free IP Project //-- Verilog Free-CORDIC Core //-- (c) 2000, The Free IP Project and Rohit Sharma (srohit@free-ip.com) //-- //-- //-- FREE IP GENERAL PUBLIC LICENSE //-- TERMS AND CONDITIONS FOR USE, COPYING, DISTRIBUTION, AND MODIFICATION //-- //-- 1. You may copy and distribute verbatim copies of this core, as long //-- as this file, and the other associated files, remain intact and //-- unmodified. Modifications are outlined below. //-- 2. You may use this core in any way, be it academic, commercial, or //-- military. Modified or not. //-- 3. Distribution of this core must be free of charge. Charging is //-- allowed only for value added services. Value added services //-- would include copying fees, modifications, customizations, and //-- inclusion in other products. //-- 4. If a modified source code is distributed, the original unmodified //-- source code must also be included (or a link to the Free IP web //-- site). In the modified source code there must be clear //-- identification of the modified version. //-- 5. Visit the Free IP web site for additional information. //-- http://www.free-ip.com //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- INTRODUCTION The CORDIC (COordinate Rotation Digital Computing) algorithm is a time and space efficient algorithm mainly used for calculate the Sine and Cosine of a given angle. It can also be used for computing log, exponent and square root. Common uses are sine and cosine generation, vector magnitude, polar- cartesian conversions, and vector rotation. The Free-CORDIC core is a parameterized Verilog RTL code for a 16 bit fixed point CORDIC. The input to this system is 17 bit angle in degrees (signed magnitude representation) and output is 17 bit sine and cosine values. The time efficiency in this algorithm is brought about by the replacement of multiplication/division operation by shift operation. Hence the only costly operation left is addition. So adders are the heart of CORDIC architecture. The Free-CORDIC core uses three different adders, i.e. CLA (Carry Look-ahead Adder), RCA (Ripple Carry Adder)and a combination of CLA and RCA. Combination of CLA and RCA means small sets of CLAs connected through rippling carry-out and carry-ins. All the three architectures have their area versus efficiency trade-offs. Generally, CLA based CORDIC has minimum area but slower in speed in comparision to other two CORDIC architectures, whereas segmented CLA based CORDIC gives best performance with area panelty. APPLICATIONS o 16 bit fixed point arithmetic. o Input angle range -45 degrees to +45 degrees. o Input angle value: signed magnitude representation (1 sign bit, 8 integer bits, 8 fractional bits). o Output values in 2's complement representation. o Synchronous reset. o Parameterized Verilog RTL code with sample synthesis script (For Synopsys DC). INTERFACE Verilog instantiation in oc the free-CORDIC would look like this. cordic cordicInstance (CosX,SinX,theta,Sign,clock,reset); SIGNAL DECLARATION clock | Input | The main system clock. All synchronous signals are clocked off the rising edge of clk. reset | Input | An active high synchronous reset signal. Sign | Input | Sign bit for the input Angle. theta | Input | 16 bit input in degrees (8 integer bits, 8 fractional bits). CosX | Output | 17 bit output value (1 bit sign and 16 bit value) of Cos(theta) in 2's complement representation. Valid only after 16 clock cycle from reset goes low. SinX | Output | 17 bit output value (1 bit sign and 16 bit value) of Sin(theta) in 2's complement representation. Valid only after 16 clock cycle from reset goes low. CONTENTS After unzipping, you shall see the following directories and subdirectories. README : this file. cla/ : CORDIC uding carry look ahead adder. hdl/ : verilog RTL code. script/ : sample script for synthesis. cla.rca/ : CORDIC uding carry look ahead and ripple carry adder. hdl/ : verilog RTL code. script/ : sample script for synthesis. cla/ : CORDIC uding carry look ahead adder. hdl/ : verilog RTL code. script/ : sample script for synthesis. SIMULATION file sim.txt (present under each hdl/ directory) contains the file names exactly the order the simulator should see. For example, with verilog-XL issue the\ following commands to get the simulattion results. > cd cla/hdl > verilog -f sim.txt SYNTHESIS see the sample script */script/syn.scr under each directory. If you have any more questions, free free to drop me a mail at srohit@free-ip.com. HISTORY v0.1 - The inital release (May, 2000)

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