文件列表:

uart IP Core (0, 2012-09-09)
uart IP Core\bench (0, 2012-09-09)
uart IP Core\bench\CVS (0, 2012-09-09)
uart IP Core\bench\CVS\Entries (25, 2008-05-14)
uart IP Core\bench\CVS\Repository (16, 2008-05-14)
uart IP Core\bench\CVS\Root (13, 2008-05-14)
uart IP Core\bench\verilog (0, 2012-09-09)
uart IP Core\bench\verilog\CVS (0, 2012-09-09)
uart IP Core\bench\verilog\CVS\Entries (653, 2008-05-14)
uart IP Core\bench\verilog\CVS\Repository (24, 2008-05-14)
uart IP Core\bench\verilog\CVS\Root (13, 2008-05-14)
uart IP Core\bench\verilog\test_cases (0, 2012-09-09)
uart IP Core\bench\verilog\test_cases\CVS (0, 2012-09-09)
uart IP Core\bench\verilog\test_cases\CVS\Entries (45, 2008-05-14)
uart IP Core\bench\verilog\test_cases\CVS\Repository (35, 2008-05-14)
uart IP Core\bench\verilog\test_cases\CVS\Root (13, 2008-05-14)
uart IP Core\bench\verilog\test_cases\uart_int.v (8650, 2004-03-27)
uart IP Core\bench\verilog\uart_device.v (23052, 2004-03-27)
uart IP Core\bench\verilog\uart_device_utilities.v (11677, 2004-03-27)
uart IP Core\bench\verilog\uart_log.v (7057, 2004-03-27)
uart IP Core\bench\verilog\uart_test.v (10875, 2004-03-27)
uart IP Core\bench\verilog\uart_testbench.v (46481, 2004-03-27)
uart IP Core\bench\verilog\uart_testbench_defines.v (9780, 2004-03-27)
uart IP Core\bench\verilog\uart_testbench_utilities.v (10882, 2004-03-27)
uart IP Core\bench\verilog\uart_wb_utilities.v (13562, 2004-03-27)
uart IP Core\bench\verilog\vapi.log (5237, 2002-01-25)
uart IP Core\bench\verilog\wb_mast.v (11508, 2001-12-04)
uart IP Core\bench\verilog\wb_master_model.v (28682, 2004-03-27)
uart IP Core\bench\verilog\wb_model_defines.v (4493, 2004-03-27)
uart IP Core\bench\vhdl (0, 2012-09-09)
uart IP Core\bench\vhdl\.keepme (0, 2001-08-13)
uart IP Core\bench\vhdl\CVS (0, 2012-09-09)
uart IP Core\bench\vhdl\CVS\Entries (42, 2008-05-14)
uart IP Core\bench\vhdl\CVS\Repository (21, 2008-05-14)
uart IP Core\bench\vhdl\CVS\Root (13, 2008-05-14)
uart IP Core\CVS (0, 2012-09-09)
uart IP Core\CVS\Entries (96, 2008-05-14)
uart IP Core\CVS\Repository (10, 2008-05-14)
uart IP Core\CVS\Root (13, 2008-05-14)
... ...

////////////////////////////////////////////////////////////////////// //// //// //// readme.txt //// //// //// //// //// //// This file is part of the "UART 16550 compatible" project //// //// http://www.opencores.org/projects/uart16550/ //// //// //// //// Documentation related to this project: //// //// http://www.opencores.org/projects/uart16550/ //// //// //// //// Projects compatibility: //// //// - WISHBONE //// //// RS232 Protocol //// //// 16550D uart (mostly supported) //// //// //// //// Overview (main Features): //// //// Device interface for testing purposes //// //// //// //// Known problems (limits): //// //// //// //// To Do: //// //// Nothing. //// //// //// //// Author(s): //// //// - Igor Mohor (igorm@opencores.org) //// //// //// //// Created and updated: (See log for the revision history) //// //// //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2001 Authors //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: readme.txt,v $ // Revision 1.1 2002/01/25 08:54:56 mohor // UART PHY added. Files are fully operational, working on HW. // // // // // Following files are making an UART16550 PHY and are used for testing: uart_device_if_defines.v - defines related to PHY uart_device_if_memory.v - Module for initializing PHY (reading commands from vapi.log file) uart_device_if.v - Uart PHY with additional feature for testing vapi.log - File with commands (expected data, data to be send, etc.) readme.txt - This file OPERATION: uart_device_if.v is a uart PHY and connects to the uart_top.v. PHY takes commands from vapi.log file. Depending on command it can: - set a mode (5, 6, 7, 8-bit, parity, stop bits, etc.) - set a frequency divider (dll) - send a character - receive a character and compare it to the expected one - send a glitch (after a certain period of time) - send a break - detect a break - Check if fifo is empty/not empty (and generate an error if expected value differs from actual) - delay (does nothing for certain number of characters) On the other side of uart some kind of host must be connected that controls the phy. This is the structure: |||||||||||||| |||||||||||||||| |||||||||||||||| | | | | | | | Host | <----------> | UART | <----------> | PHY | | | | | | | |||||||||||||| |||||||||||||||| |||||||||||||||| PHY must know how host sets th UART and work in the same mode. Besides that it must know what host is sending or expecting to receive. Operation of the PHY must be written in the vapi.log file. When I was using this testing environment, I used OpenRISC1200 as a host. Everything is fully operational. UART was also tested in hardware (on two different boards), running uCLinux in both, interrupt and polling mode.

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