文件列表:

RD1012_rev01.2\docs (0, 2011-03-31)
RD1012_rev01.2\docs\rd1012.pdf (304521, 2011-03-31)
RD1012_rev01.2\project (0, 2011-03-25)
RD1012_rev01.2\project\4k (0, 2011-03-25)
RD1012_rev01.2\project\4k\verilog (0, 2011-03-25)
RD1012_rev01.2\project\4k\verilog\8b_10b_enc_dec.lct (1749, 2010-06-24)
RD1012_rev01.2\project\4k\vhdl (0, 2011-03-25)
RD1012_rev01.2\project\4k\vhdl\8b_10b_enc_dec.lct (1813, 2010-06-24)
RD1012_rev01.2\project\ecp_ec (0, 2011-03-25)
RD1012_rev01.2\project\ecp_ec\verilog (0, 2011-03-25)
RD1012_rev01.2\project\ecp_ec\verilog\8b_10b_enc_dec.lpf (96, 2011-01-31)
RD1012_rev01.2\project\ecp_ec\vhdl (0, 2011-03-25)
RD1012_rev01.2\project\ecp_ec\vhdl\8b_10b_enc_dec.lpf (96, 2010-06-23)
RD1012_rev01.2\project\ecp2m (0, 2011-03-25)
RD1012_rev01.2\project\ecp2m\verilog (0, 2011-03-25)
RD1012_rev01.2\project\ecp2m\verilog\enc_dec.lpf (81, 2011-01-31)
RD1012_rev01.2\project\ecp2m\verilog\Strategy1.sty (304, 2011-01-31)
RD1012_rev01.2\project\ecp2m\vhdl (0, 2011-03-25)
RD1012_rev01.2\project\ecp2m\vhdl\enc_dec.lpf (81, 2011-01-31)
RD1012_rev01.2\project\ecp2m\vhdl\Strategy1.sty (133, 2011-03-25)
RD1012_rev01.2\project\ecp3 (0, 2011-03-25)
RD1012_rev01.2\project\ecp3\verilog (0, 2011-03-25)
RD1012_rev01.2\project\ecp3\verilog\enc_dec.lpf (81, 2011-01-31)
RD1012_rev01.2\project\ecp3\verilog\Strategy1.sty (231, 2011-02-25)
RD1012_rev01.2\project\ecp3\vhdl (0, 2011-03-25)
RD1012_rev01.2\project\ecp3\vhdl\enc_dec.lpf (81, 2011-03-29)
RD1012_rev01.2\project\ecp3\vhdl\Strategy1.sty (133, 2011-03-24)
RD1012_rev01.2\project\xo (0, 2011-03-25)
RD1012_rev01.2\project\xo\verilog (0, 2011-03-25)
RD1012_rev01.2\project\xo\verilog\8b_10b_enc_dec.lpf (97, 2010-06-21)
RD1012_rev01.2\project\xo\vhdl (0, 2011-03-25)
RD1012_rev01.2\project\xo\vhdl\8b_10b_enc_dec.lpf (97, 2010-06-22)
RD1012_rev01.2\project\xo2 (0, 2011-03-25)
RD1012_rev01.2\project\xo2\verilog (0, 2011-03-25)
RD1012_rev01.2\project\xo2\verilog\enc_dec.lpf (81, 2011-03-31)
RD1012_rev01.2\project\xo2\verilog\Strategy1.sty (625, 2011-01-31)
RD1012_rev01.2\project\xo2\vhdl (0, 2011-03-25)
RD1012_rev01.2\project\xo2\vhdl\enc_dec.lpf (79, 2011-03-31)
RD1012_rev01.2\project\xo2\vhdl\Strategy1.sty (133, 2011-03-25)
... ...

8b/10b Encoder/Decoder Reference Design =============================================================================== File List (126 files) 1. /docs/rd1012.pdf --> 8b/10b Encoder/Decoder reference design document /docs/rd1012_readme.txt --> Read me file (this file) 2. /project/4k/verilog/8b_10b_enc_dec.lct --> preference file /project/4k/vhdl/8b_10b_enc_dec.lct --> preference file /project/ecp_ec/verilog/8b_10b_enc_dec.lpf --> preference file /project/ecp_ec/vhdl/8b_10b_enc_dec.lpf --> preference file /project/ecp2m/verilog/enc_dec.lpf --> preference file /project/ecp2m/verilog/Strategy1.sty --> strategy file /project/ecp2m/vhdl/enc_dec.lpf --> preference file /project/ecp2m/vhdl/Strategy1.sty --> strategy file /project/ecp3/verilog/enc_dec.lpf --> preference file /project/ecp3/verilog/Strategy1.sty --> strategy file /project/ecp3/vhdl/enc_dec.lpf --> preference file /project/ecp3/vhdl/Strategy1.sty --> strategy file /project/xo/verilog/8b_10b_enc_dec.lpf --> preference file /project/xo/vhdl/8b_10b_enc_dec.lpf --> preference file /project/xo2/verilog/enc_dec.lpf --> preference file /project/xo2/verilog/Strategy1.sty --> strategy file /project/xo2/vhdl/enc_dec.lpf --> preference file /project/xo2/vhdl/Strategy1.sty --> strategy file /project/xp2/verilog/enc_dec.lpf --> preference file /project/xp2/verilog/Strategy1.sty --> strategy file /project/xp2/vhdl/enc_dec.lpf --> preference file /project/xp2/vhdl/Strategy1.sty --> strategy file 3. /simulation/4k/verilog/tb_top_net_8b/10b_tffa.udo --> script for functional simulation with Active HDL /simulation/4k/verilog/tb_top_net_8b/10b_tfa.udo --> script for timing simulation with Active HDL /simulation/4k/vhdl/tb_top_net_8b/10b_vhdaf.udo --> script for functional simulation with Active HDL /simulation/4k/vhdl/tb_top_net_8b/10b_vhda.udo --> script for timing simulation with Active HDL /simulation/ecp_ec/verilog/tb_top_net_8b/10b_tff.udo --> script for functional simulation with Active HDL /simulation/ecp_ec/verilog/tb_top_net_8b/10b_tf.udo --> script for timing simulation with Active HDL /simulation/ecp_ec/vhdl/tb_top_net_8b/10b_vhdf.udo --> script for functional simulation with Active HDL /simulation/ecp_ec/vhdl/tb_top_net_8b/10b_vhd.udo --> script for timing simulation with Active HDL /simulation/ecp2m/verilog/rtlsim.do --> script for functional simulation with Active HDL /simulation/ecp2m/verilog/timesim.do --> script for timing simulation with Active HDL /simulation/ecp2m/verilog/enc_dec_enc_dec_vo.*** --> verilog timing simulation file /simulation/ecp2m/verilog/enc_dec_enc_dec_vo.vo --> verilog timing simulation netlist /simulation/ecp2m/vhdl/rtlsim.do --> script for functional simulation with Active HDL /simulation/ecp2m/vhdl/timesim.do --> script for timing simulation with Active HDL /simulation/ecp2m/vhdl/enc_dec_enc_dec_vho.*** --> vhdl timing simulation file /simulation/ecp2m/vhdl/enc_dec_enc_dec_vho.vho --> vhdl timing simulation netlist /simulation/ecp3/verilog/rtlsim.do --> script for functional simulation with Active HDL /simulation/ecp3/verilog/timesim.do --> script for timing simulation with Active HDL /simulation/ecp3/verilog/enc_dec_enc_dec_vo.*** --> verilog timing simulation file /simulation/ecp3/verilog/enc_dec_enc_dec_vo.vo --> verilog timing simulation netlist /simulation/ecp3/vhdl/rtlsim.do --> script for functional simulation with Active HDL /simulation/ecp3/vhdl/timesim.do --> script for timing simulation with Active HDL /simulation/ecp3/vhdl/enc_dec_enc_dec_vho.*** --> vhdl timing simulation file /simulation/ecp3/vhdl/enc_dec_enc_dec_vho.vho --> vhdl timing simulation netlist /simulation/xo/verilog/tb_top_net_8b/10b_tff.udo --> script for functional simulation with Active HDL /simulation/xo/verilog/tb_top_net_8b/10b_tf.udo --> script for timing simulation with Active HDL /simulation/xo/vhdl/tb_top_net_8b/10b_vhdf.udo --> script for functional simulation with Active HDL /simulation/xo/vhdl/tb_top_net_8b/10b_vhd.udo --> script for timing simulation with Active HDL /simulation/xo2/verilog/rtlsim.do --> script for functional simulation with Active HDL /simulation/xo2/verilog/timesim.do --> script for timing simulation with Active HDL /simulation/xo2/verilog/enc_dec_enc_dec_vo.*** --> verilog timing simulation file /simulation/xo2/verilog/enc_dec_enc_dec_vo.vo --> verilog timing simulation netlist /simulation/xo2/vhdl/rtlsim.do --> script for functional simulation with Active HDL /simulation/xo2/vhdl/timesim.do --> script for timing simulation with Active HDL /simulation/xo2/vhdl/enc_dec_enc_dec_vho.*** --> vhdl timing simulation file /simulation/xo2/vhdl/enc_dec_enc_dec_vho.vho --> vhdl timing simulation netlist /simulation/xp2/verilog/tb_top_net_8b/10b_tff.udo --> script for functional simulation with Active HDL /simulation/xp2/verilog/tb_top_net_8b/10b_tf.udo --> script for timing simulation with Active HDL /simulation/xp2/vhdl/tb_top_net_8b/10b_vhdf.udo --> script for functional simulation with Active HDL /simulation/xp2/vhdl/tb_top_net_8b/10b_vhd.udo --> script for timing simulation with Active HDL 4. /source/4k/verilog/enc_8b10b.bl1 --> netlist file /source/4k/verilog/dec_10b8b.bl1 --> netlist file /source/4k/verilog/enc_dec.v --> encoder/decoder definition file /source/4k/verilog/top_net_8b10b.v --> top level source file /source/4k/vhdl/enc_8b10b.ngo --> netlist file /source/4k/vhdl/dec_10b8b.ngo --> netlist file /source/4k/vhdl/enc_dec.v --> encoder/decoder definition file /source/4k/vhdl/top_net_8b10b_cpld.vhd --> top level source file /source/ecp_ec/verilog/enc_8b10b.ngo --> netlist file /source/ecp_ec/verilog/dec_10b8b.ngo --> netlist file /source/ecp_ec/verilog/enc_dec.v --> encoder/decoder definition file /source/ecp_ec/verilog/top_net_8b10b.v --> top level source file /source/ecp_ec/vhdl/enc_8b10b.ngo --> netlist file /source/ecp_ec/vhdl/dec_10b8b.ngo --> netlist file /source/ecp_ec/vhdl/enc_dec.v --> encoder/decoder definition file /source/ecp_ec/vhdl/top_net_8b10b.vhd --> top level source file /source/ecp2m/verilog/enc_8b10b.ngo --> netlist file /source/ecp2m/verilog/dec_10b8b.ngo --> netlist file /source/ecp2m/verilog/enc_dec.v --> encoder/decoder definition file /source/ecp2m/verilog/top_net_8b10b.v --> top level source file /source/ecp2m/vhdl/enc_8b10b.ngo --> netlist file /source/ecp2m/vhdl/dec_10b8b.ngo --> netlist file /source/ecp2m/vhdl/enc_dec.v --> encoder/decoder definition file /source/ecp2m/vhdl/top_net_8b10b.vhd --> top level source file /source/ecp3/verilog/enc_8b10b.ngo --> netlist file /source/ecp3/verilog/dec_10b8b.ngo --> netlist file /source/ecp3/verilog/enc_dec.v --> encoder/decoder definition file /source/ecp3/verilog/top_net_8b10b.v --> top level source file /source/ecp3/vhdl/enc_8b10b.ngo --> netlist file /source/ecp3/vhdl/dec_10b8b.ngo --> netlist file /source/ecp3/vhdl/enc_dec.v --> encoder/decoder definition file /source/ecp3/vhdl/top_net_8b10b.vhd --> top level source file /source/xo/verilog/enc_8b10b.ngo --> netlist file /source/xo/verilog/dec_10b8b.ngo --> netlist file /source/xo/verilog/enc_dec.v --> encoder/decoder definition file /source/xo/verilog/top_net_8b10b.v --> top level source file /source/xo/vhdl/enc_8b10b.ngo --> netlist file /source/xo/vhdl/dec_10b8b.ngo --> netlist file /source/xo/vhdl/enc_dec.v --> encoder/decoder definition file /source/xo/vhdl/top_net_8b10b.vhd --> top level source file /source/xo2/verilog/enc_8b10b.ngo --> netlist file /source/xo2/verilog/dec_10b8b.ngo --> netlist file /source/xo2/verilog/enc_dec.v --> encoder/decoder definition file /source/xo2/verilog/top_net_8b10b.v --> top level source file /source/xo2/vhdl/enc_8b10b.ngo --> netlist file /source/xo2/vhdl/dec_10b8b.ngo --> netlist file /source/xo2/vhdl/enc_dec.v --> encoder/decoder definition file /source/xo2/vhdl/top_net_8b10b.vhd --> top level source file /source/xp2/verilog/enc_8b10b.ngo --> netlist file /source/xp2/verilog/dec_10b8b.ngo --> netlist file /source/xp2/verilog/enc_dec.v --> encoder/decoder definition file /source/xp2/verilog/top_net_8b10b.v --> top level source file /source/xp2/vhdl/enc_8b10b.ngo --> netlist file /source/xp2/vhdl/dec_10b8b.ngo --> netlist file /source/xp2/vhdl/enc_dec.v --> encoder/decoder definition file /source/xp2/vhdl/top_net_8b10b.vhd --> top level source file 5. /testbench/4k_ecp_xo_xp2/verilog/tb_top_net_8b10b.v --> Testbench for simulation /testbench/4k_ecp_xo_xp2/vhdl/tb_top_net_8b10b.vhd --> Testbench for simulation /testbench/ecp2m_ecp3/verilog/tb_top_net_8b10b.v --> Testbench for simulation /testbench/ecp2m_ecp3/vhdl/tb_top_net_8b10b.vhd --> Testbench for simulation /testbench/xo2/verilog/tb_top_net_8b10b.v --> Testbench for simulation /testbench/xo2/vhdl/tb_top_net_8b10b.vhd --> Testbench for simulation =================================================================================================== Using ispLEVER Classic Software --------------------------------------------------------------------------------------------------- How to bring up the project: 1. Unzip the RD1012_revyy.y.zip file using the existing folder names, where yy.y is the current version of the zip file 2. Bring up ispLEVER Classic 1.4 Project Navigator 3. In the File menu, click on new Project, create a directory for 4k device. Then browse to the directory where the souce files and testbench file are placed. How to run simulation: 1. In the Project Navigator, highlight the ..\..\..\testbench\\tb_top_net_8b10b.v or tb_top_net_8b10b.vhd file on the left-side panel, user will see 3 simulation options on the right panel 2. For functional simulation, double click on Verilog Functional Simulation with Aldec Active-HDL. Aldec simulator will be brought up, click yes to overwrite the existing file 3. Functional simulation will run until complete. user will see a script shown in the Console panel like this: # KERNEL: TEST BENCH: Testing started # KERNEL: TEST BENCH: Testing 32 different '000_EDCBA' Data values with Current RD- started at time 41.174 ns # KERNEL: TEST BENCH: Testing 32 different '000_EDCBA' Data values with Current RD+ started at time 3799.772 ns # KERNEL: TEST BENCH: Testing 8 different 'HGF_00000' Data values with Current RD- started at time 7940.7 ns # KERNEL: TEST BENCH: Testing 8 different 'HGF_00000' Data values with Current RD+ started at time 8881.82 ns # KERNEL: TEST BENCH: Testing 256 different 'HGF_EDCBA' Data values with Current RD- started at time 9917.052 ns # KERNEL: TEST BENCH: Testing 256 different 'HGF_EDCBA' Data values with Current RD+ started at time 40032.892 ns # KERNEL: TEST BENCH: Testing 32 different '000_EDCBA' Control values with Current RD- started at time 73160.316 ns # KERNEL: TEST BENCH: Testing 32 different '000_EDCBA' Control values with Current RD+ started at time 76924.796 ns # KERNEL: TEST BENCH: Testing 8 different 'HGF_00000' Control values with Current RD- started at time 81065.724 ns # KERNEL: TEST BENCH: Testing 8 different 'HGF_00000' Control values with Current RD+ started at time 82006.844 ns # KERNEL: TEST BENCH: Testing 256 different 'HGF_EDCBA' Control values with Current RD- started at time 83042.076 ns # KERNEL: TEST BENCH: Testing 256 different 'HGF_EDCBA' Control values with Current RD+ started at time 113157.916 ns # KERNEL: TEST BENCH: Testing completed at time 153343.74 ns # EXECUTION:: NOTE : ---------- END OF SIMULATION ---------- # EXECUTION:: Time: 153343740 ps, Iteration: 1, TOP instance, Process: line__480. # KERNEL: stopped at time: 155 us 4. For timing simulation, double click on Verilog Post-Route Timing Simulation with Aldec Active-HDL. Similar message will be shown in the console panel of the Aldec Active-HDL simulator. =================================================================================================== Using Diamond Software --------------------------------------------------------------------------------------------------- HOW TO CREATE A PROJECT IN DIAMOND: 1. Launch Diamond software, in the GUI, select File >> New Project, click Next 2. In the New Project popup, select the Project location and provide a Project name and implementation name, click Next. 3. Add the necessary source files from the RD1010\source directory, click Next 4. Select the desired part and speedgrade. You may use RD1010.pdf to see which device and speedgrade can be selected to achieve the published timing result 5. Click Finish. Now the project is successfully created. 6. MAKE SURE the provided lpf and/or sty files are used in the current directory. ---------------------------------------------------------------------------------------------------- HOW TO RUN SIMULATION UNDER DIAMOND: 1. Bring up the Simulation Wizard under the Tools menu 2. Next provide a name for simulation project. 2.1 For post-route simulation, must export verilog or vhdl simulation file after Place and Route 3. Next add the test bench files from the RD1012\TestBench directory & source files from RD1012\Source directory for Function Simation & exported post-route netlist file for Timing Simulation. 3.1 For VHDL, make sure the top-level test bench is last to be added 4. Next click Finish, this will bring up the Aldec simulator automatically 5. In Aldec environment, you can manually activate the simulation or you can use a script 5.1 Use the provided script in the RD1010\Simulation\ directory a. For functional simulation, change the library name to the device family i) MachXO2: ovi_machxo2 for verilog, machxo2 for vhdl ii) MachXO: ovi_machxo for verilog, machxo for vhdl iii)XP2: ovi_xp2 for verilog, xp2 for vhdl iv) ECP2M: ovi_ecp2m for verilog, ecp2m for vhdl v) ECP3: ovi_ecp3 for verilog, ecp3 for vhdl b. For POST-ROUTE timing simulation, open the script and change the following: i) The *** file name and the path pointing to your *** file. The path usually looks like ".//<***_file_name>.***" ii) Change the library name using the library name described above c. Click Tools > Execute Macro and select the xxx.do file to run the simulation d. This will run the simulation until finish 5.2 Manually activate the simulation a. Click Simulation > Initialize Simulation b. Click File > New > Waveform, this will bring up the Waveform panel c. Click on the top-level testbench, drag all the signals into the Waveform panel d. At the Console panel, type "run -all" for VHDL simulation, or "run -all" for Verilog simulation e. For timing simulation, you must manually add -***max UUT="./final_xo2/final_xo2_final_xo2_vo.***" into the asim or vsim command. Use the command in timing_xxx.do as an example 6. The simulation result will be similar to the one described in ispLEVER simulation section.

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