DE2_70_NIOS_10_flash
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：1583KB
下载次数：8
上传日期：2012-10-06 22:44:21
上 传 者：
初春的雪
说明： 首先将此Verilog程序下载到DE2-70开发板上后，然后用NiosII软件将任何文件的二进制数据写入到ssram或者sdram等存储器重去，并可以指定起始地址。
(First program this Verilog downloaded to the DE2-70 development board, and then the use NiosII software binary data of any file written to memory such as ssram or sdram weight go, and you can specify a starting address.)
文件列表:
DE2_70_NIOS_10_flash (0, 2008-10-19)
DE2_70_NIOS_10_flash\.sopc_builder (0, 2008-10-19)
DE2_70_NIOS_10_flash\.sopc_builder\install.ptf (19632, 2008-10-19)
DE2_70_NIOS_10_flash\.sopc_builder\install2.ptf (5734, 2008-10-19)
DE2_70_NIOS_10_flash\.sopc_builder\preferences.xml (815, 2008-10-19)
DE2_70_NIOS_10_flash\AUDIO.v (2664, 2008-10-19)
DE2_70_NIOS_10_flash\DE2_70.qpf (908, 2008-10-18)
DE2_70_NIOS_10_flash\DE2_70.qsf (28469, 2008-10-19)
DE2_70_NIOS_10_flash\DE2_70.qws (198, 2008-10-19)
DE2_70_NIOS_10_flash\DE2_70_SOPC_sim (0, 2008-10-19)
DE2_70_NIOS_10_flash\DE2_70_SOPC_sim\atail-f.pl (4677, 2008-10-18)
DE2_70_NIOS_10_flash\DE2_70_SOPC_sim\contents_file_warning.txt (247, 2008-10-18)
DE2_70_NIOS_10_flash\DE2_70_SOPC_sim\dummy_file (0, 2008-09-10)
DE2_70_NIOS_10_flash\DE2_70_SOPC_sim\jtag_uart_input_mutex.dat (3, 2008-10-18)
DE2_70_NIOS_10_flash\DE2_70_SOPC_sim\jtag_uart_input_stream.dat (10, 2008-10-18)
DE2_70_NIOS_10_flash\DE2_70_SOPC_sim\jtag_uart_output_stream.dat (0, 2007-10-05)
DE2_70_NIOS_10_flash\DE2_70_SOPC_sim\uart_input_data_mutex.dat (3, 2008-10-18)
DE2_70_NIOS_10_flash\DE2_70_SOPC_sim\uart_input_data_stream.dat (7, 2008-10-18)
DE2_70_NIOS_10_flash\DE2_70_SOPC_sim\uart_log_module.txt (0, 2007-10-05)
DE2_70_NIOS_10_flash\DM9000A.v (3993, 2008-10-19)
DE2_70_NIOS_10_flash\IP (0, 2008-10-19)
DE2_70_NIOS_10_flash\IP\TERASIC_AUDIO (0, 2008-10-19)
DE2_70_NIOS_10_flash\IP\TERASIC_AUDIO\hdl (0, 2008-10-19)
DE2_70_NIOS_10_flash\IP\TERASIC_AUDIO\hdl\AUDIO_ADC.v (4536, 2007-10-05)
DE2_70_NIOS_10_flash\IP\TERASIC_AUDIO\hdl\AUDIO_DAC.v (4664, 2007-10-05)
DE2_70_NIOS_10_flash\IP\TERASIC_AUDIO\hdl\AUDIO_IF.v (6944, 2007-10-05)
DE2_70_NIOS_10_flash\IP\TERASIC_AUDIO\hdl\AUDIO_IF.v.bak (6607, 2007-10-04)
DE2_70_NIOS_10_flash\IP\TERASIC_AUDIO\hdl\AUDIO_IF_hw.tcl (2227, 2007-10-05)
DE2_70_NIOS_10_flash\IP\TERASIC_AUDIO\hdl\audio_fifo.v (7121, 2007-09-27)
DE2_70_NIOS_10_flash\IP\TERASIC_AUDIO\hdl\audio_fifo_wave0.jpg (108469, 2007-09-27)
DE2_70_NIOS_10_flash\IP\TERASIC_AUDIO\hdl\audio_fifo_wave1.jpg (96028, 2007-09-27)
DE2_70_NIOS_10_flash\IP\TERASIC_AUDIO\hdl\audio_fifo_waveforms.html (1111, 2007-09-27)
DE2_70_NIOS_10_flash\IP\TERASIC_AUDIO\software (0, 2008-10-19)
DE2_70_NIOS_10_flash\IP\TERASIC_AUDIO\software\AUDIO.c (10344, 2007-09-28)
DE2_70_NIOS_10_flash\IP\TERASIC_AUDIO\software\AUDIO.h (1409, 2007-09-28)
DE2_70_NIOS_10_flash\IP\TERASIC_AUDIO\software\AUDIO_REG.h (753, 2007-09-29)
DE2_70_NIOS_10_flash\IP\TERASIC_Binary_VGA_Controller (0, 2008-10-19)
DE2_70_NIOS_10_flash\IP\TERASIC_Binary_VGA_Controller\hdl (0, 2008-10-19)
DE2_70_NIOS_10_flash\IP\TERASIC_Binary_VGA_Controller\hdl\Binary_VGA_Control_IF_hw.tcl (2913, 2007-10-05)
DE2_70_NIOS_10_flash\IP\TERASIC_Binary_VGA_Controller\hdl\Binary_VGA_Control_IF_hw.tcl~ (2913, 2007-10-05)
... ...
Readme - Hello World Software Example
DESCRIPTION:
Simple program that prints "Hello from Nios II"
REQUIREMENTS:
This example will run on the following Nios II designs, targeting the Nios
Stratix & Cyclone development boards:
- Standard
- Full Featured
- Fast
- Low Cost
The memory footprint of this hosted application is ~69 kbytes by default
using the standard reference deisgn.
For a reduced footprint version of this template, and an explanation of how
to reduce the memory footprint for a given application, see the
"small_hello_world" template.
PERIPHERALS USED:
This example exercises the following peripherals:
- STDOUT device (UART or JTAG UART)
SOFTWARE SOURCE FILES:
This example includes the following software source files:
- hello_world.c: Everyone needs a Hello World program, right?
BOARD/HOST REQUIREMENTS:
This example requires only a JTAG connection with a Nios Development board. If
the host communication settings are changed from JTAG UART (default) to use a
conventional UART, a serial cable between board DB-9 connector and the host is
required.
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