jtag_uart
所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:13125KB
下载次数:8
上传日期:2012-10-07 10:38:20
上 传 者:
初春的雪
说明: (2)实验2:JTAG UART通信实验,完整的设计工程文件在jtag_uart文件夹下
((2) Experiment 2: the JTAG UART communication experiment, complete design engineering the file in jtag_uart file folder)
文件列表:
jtag_uart (0, 2012-10-07)
jtag_uart\.sopc_builder (0, 2012-10-07)
jtag_uart\.sopc_builder\install.ptf (11692, 2009-12-27)
jtag_uart\.sopc_builder\install2.ptf (4917, 2009-12-27)
jtag_uart\.sopc_builder\preferences.xml (621, 2009-12-18)
jtag_uart\DE2_pin.tcl (20274, 2009-06-09)
jtag_uart\altpll0.bsf (2991, 2009-12-18)
jtag_uart\altpll0.ppf (355, 2009-12-18)
jtag_uart\altpll0.qip (448, 2009-12-18)
jtag_uart\altpll0.v (14502, 2009-12-18)
jtag_uart\altpll0_bb.v (10930, 2009-12-18)
jtag_uart\altpll0_wave0.jpg (39539, 2009-12-18)
jtag_uart\altpll0_waveforms.html (620, 2009-12-18)
jtag_uart\cpu.ocp (840, 2009-12-18)
jtag_uart\cpu.sdc (3992, 2009-12-18)
jtag_uart\cpu.v (410264, 2009-12-18)
jtag_uart\cpu_bht_ram.mif (2392, 2009-12-18)
jtag_uart\cpu_dc_tag_ram.mif (856, 2009-12-18)
jtag_uart\cpu_ic_tag_ram.mif (1881, 2009-12-18)
jtag_uart\cpu_jtag_debug_module_sysclk.v (6332, 2009-12-18)
jtag_uart\cpu_jtag_debug_module_tck.v (7700, 2009-12-18)
jtag_uart\cpu_jtag_debug_module_wrapper.v (9332, 2009-12-18)
jtag_uart\cpu_mult_cell.v (6103, 2009-12-18)
jtag_uart\cpu_ociram_default_contents.mif (5878, 2009-12-18)
jtag_uart\cpu_rf_ram_a.mif (600, 2009-12-18)
jtag_uart\cpu_rf_ram_b.mif (600, 2009-12-18)
jtag_uart\cpu_test_bench.v (39245, 2009-12-18)
jtag_uart\db (0, 2012-10-07)
jtag_uart\db\a_dpfifo_8t21.tdf (3251, 2009-12-18)
jtag_uart\db\a_fefifo_7cf.tdf (3892, 2009-12-18)
jtag_uart\db\altsyncram_0jb1.tdf (28845, 2009-12-18)
jtag_uart\db\altsyncram_29f1.tdf (40876, 2009-12-18)
jtag_uart\db\altsyncram_6jb1.tdf (28845, 2009-12-18)
jtag_uart\db\altsyncram_9tl1.tdf (12554, 2009-12-18)
jtag_uart\db\altsyncram_9vc1.tdf (38031, 2009-12-18)
jtag_uart\db\altsyncram_e502.tdf (44611, 2009-12-18)
jtag_uart\db\altsyncram_j9f1.tdf (22228, 2009-12-18)
jtag_uart\db\altsyncram_kib1.tdf (28841, 2009-12-18)
jtag_uart\db\altsyncram_p2f1.tdf (40402, 2009-12-18)
jtag_uart\db\altsyncram_pkf1.tdf (6329, 2009-12-18)
... ...
Readme - Hello World Software Example
DESCRIPTION:
Simple program that prints "Hello from Nios II"
REQUIREMENTS:
This example will run on the following Nios II designs, targeting the Nios
Stratix & Cyclone development boards:
- Standard
- Full Featured
- Fast
- Low Cost
The purpose of this example is to demonstrate the smallest possible Hello
World application, using the Nios II HAL library. The memory footprint
of this hosted application is ~332 bytes by default using the standard
reference design. For a more fully featured Hello World application
example, see the example titled "Hello World".
The memory footprint of this example has been reduced by making the
following changes to the normal "Hello World" example.
Check in the Nios II Software Developers Manual for a more complete
description.
In the SW Application project (small_hello_world):
- In the C/C++ Build page
- Set the Optimization Level to -Os
In System Library project (small_hello_world_syslib):
- In the C/C++ Build page
- Set the Optimization Level to -Os
- Define the preprocessor option ALT_NO_INSTRUCTION_EMULATION
This removes software exception handling, which means that you cannot
run code compiled for Nios II cpu with a hardware multiplier on a core
without a the multiply unit. Check the Nios II Software Developers
Manual for more details.
- In the System Library page:
- Set Periodic system timer and Timestamp timer to none
This prevents the automatic inclusion of the timer driver.
- Set Max file descriptors to 4
This reduces the size of the file handle pool.
- Uncheck Clean exit (flush buffers)
This removes the call to exit, and when main is exitted instead of
calling exit the software will just spin in a loop.
- Check Small C library
This uses a reduced functionality C library, which lacks
support for buffering, file IO, floating point and getch(), etc.
Check the Nios II Software Developers Manual for a complete list.
- Check Reduced device drivers
This uses reduced functionality drivers if they're available. For the
standard design this means you get polled UART and JTAG UART drivers,
no support for the LCD driver and you lose the ability to program
CFI compliant flash devices.
PERIPHERALS USED:
This example exercises the following peripherals:
- STDOUT device (UART or JTAG UART)
SOFTWARE SOURCE FILES:
This example includes the following software source files:
- small_hello_world.c:
BOARD/HOST REQUIREMENTS:
This example requires only a JTAG connection with a Nios Development board. If
the host communication settings are changed from JTAG UART (default) to use a
conventional UART, a serial cable between board DB-9 connector and the host is
required.
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