文件列表:

models (0, 2011-04-15)
models\T025MMSP001_1_8 (0, 2011-04-15)
models\T025MMSP005_1_7 (0, 2011-04-15)
models\T025MMSP001_1_8\T-025-MM-SP-001 (0, 2011-04-15)
models\T025MMSP005_1_7\ADS (0, 2011-04-15)
models\T025MMSP005_1_7\dat (0, 2011-04-15)
models\T025MMSP005_1_7\eldo (0, 2011-04-15)
models\T025MMSP005_1_7\hspice (0, 2011-04-15)
models\T025MMSP005_1_7\spectre (0, 2011-04-15)
models\T025MMSP001_1_8\T-025-MM-SP-001\fp1 (0, 2011-04-15)
models\T025MMSP001_1_8\T-025-MM-SP-001\fp2 (0, 2011-04-15)
models\T025MMSP001_1_8\T-025-MM-SP-001\fp3 (0, 2011-04-15)
models\T025MMSP005_1_7\dat\resistor (0, 2011-04-15)
models\T025MMSP005_1_7\dat\moscap (0, 2011-04-15)
models\T025MMSP005_1_7\dat\DATA (0, 2011-04-15)
models\T025MMSP001_1_8\T-025-MM-SP-001\fp1\ADS (0, 2011-04-15)
models\T025MMSP001_1_8\T-025-MM-SP-001\fp1\eldo (0, 2011-04-15)
models\T025MMSP001_1_8\T-025-MM-SP-001\fp1\hspice (0, 2011-04-15)
models\T025MMSP001_1_8\T-025-MM-SP-001\fp1\intercon (0, 2011-04-15)
models\T025MMSP001_1_8\T-025-MM-SP-001\fp1\spectre (0, 2011-04-15)
models\T025MMSP005_1_7\dat\DATA\xjvaractor (0, 2011-04-15)
models\T025MMSP005_1_7\dat\DATA\Mos_W5_IO (0, 2011-04-15)
models\T025MMSP005_1_7\dat\DATA\MOS_W5_core (0, 2011-04-15)
models\T025MMSP005_1_7\dat\DATA\MOS_W10_IO (0, 2011-04-15)
models\T025MMSP005_1_7\dat\DATA\mos_W10_core (0, 2011-04-15)
models\T025MMSP005_1_7\dat\DATA\mim_cap (0, 2011-04-15)
models\T025MMSP005_1_7\dat\DATA\inductor (0, 2011-04-15)
models\T025MMSP005_1_7\dat\DATA\xjvaractor\XJVaractor (0, 2011-04-15)
models\T025MMSP005_1_7\dat\DATA\Mos_W5_IO\MOS_W5_IO (0, 2011-04-15)
models\T025MMSP005_1_7\dat\DATA\MOS_W5_core\MOS_W5_Core (0, 2011-04-15)
models\T025MMSP005_1_7\dat\DATA\MOS_W10_IO\MOS_W10_IO (0, 2011-04-15)
models\T025MMSP005_1_7\dat\DATA\mos_W10_core\MOS_W10_Core (0, 2011-04-15)
models\T025MMSP005_1_7\dat\DATA\mim_cap\MIM_CAP (0, 2011-04-15)
models\T025MMSP005_1_7\dat\DATA\inductor\Inductor (0, 2011-04-15)
skill (0, 2011-04-15)
stream (0, 2011-04-15)
models\T025MMSP001_1_8\T025MMSP001_1_8.pdf (2235099, 2011-04-15)
models\T025MMSP005_1_7\T025MMSP005_1_7.pdf (1632971, 2011-04-15)
models\T025MMSP005_1_7\model1v7.doc (32257536, 2011-04-15)
... ...

TSMC 0.25UM COMS MIXED-SIGNAL 1P5M SALICIDE 2.5V/3.3V PDK V1.7 ******************************************************************************* DISCLAIMER The information contained herein is provided by TSMC on an "AS IS" basis without any warranty, and TSMC has no obligation to support or otherwise maintain the information. TSMC disclaims any representation that the information does not infringe any intellectual property rights or proprietary rights of any third parties. There are no other warranties given by TSMC, whether express, implied or statutory, including, without limitation, implied warranties of merchantability and fitness for a particular purpose. STATEMENT OF USE This information contains confidential and proprietary information of TSMC. No part of this information may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any human or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual, or otherwise, without the prior written permission of TSMC. This information was prepared for informational purpose and is for use by TSMC's customers only. TSMC reserves the right to make changes in the information at any time and without notice. ******************************************************************************* 0. Overview This PDK require the environmental variable CDS_Netlisting_Mode to be set to Analog. This PDK has been tested to work with the following software versions: Stream Version Date IC 5.033.500.3 12/08/2003 Assura 3.1.2 01/09/2004 Calibre v9.3_6.5 12/09/2003 1. Foundry Data T-025-MM-SP-005 1.7 TSMC 0.25um RF SALICIDE(1P5M+, 2.5V/3.3V) BSIM3 ( V3.2 ) SPICE ODEL T-025-MM-SP-001 1.8 TSMC 0.25um Mixed-Signal SALICIDE(1P5M+, 2.5V/3.3V) BSIM3 ( Mixed V3. 1 & V3.2 ) SPICE MODEL T-025-LO-DR-001 2.4 TSMC 0.25UM LOGIC 1P5M SALICIDE 2.5V/3.3V PROCESS DESIGN RULE T-025-MM-DR-002 2.3 TSMC 0.25UM MIXED SIGNAL 2P5M/1P5M+ SALICIDE 2.5V/3.3V PROCESS DESIGN RULE T-025-LO-LE-003 2.3a TSMC 90NM CMOS LOGIC DESIGN RULE 2. Installation of the PDK This section will guide you to install the PDK into the design environment step by step and help users to set up their environment properply. *PDK owner Step A: Download the PDK archive from TSMC Step B: Logon into the computer as the owner who will own and maintain the PDK Step C: Choose a directory that are exported to all client machines to install the PDK Step D: Install the PDK with the following unix commands: i. %mkdir ii. %cd iii. %gzip -d iv. %tar xvf **Only the owner who will maintain the PDK has the read,write and execute permission. Other users will have only read and execute access. *PDK users In the client parts(the PDK users),there are also some procedures to be followed to set up the environment properply. Step 1: Logon into the computer as the user that will use the PDK to design a Project (circuit). Step 2: Setting the environment variable "CDS_Netlisting_Mode" to "Analog" and "CDSHOME" to Cadence DFII installation path. setenv CDS_Netlisting_Mode "Analog" setenv CDSHOME Step 3: Make a directory for your design project. EX: %mkdir ~/my_circuit %cd ~/my_circuit Step 4: Create a new library for your design and add the PDK library into your reference path by adding the following line in your "cds.lib" file located in the working directory. INCLUDE /cds.lib 3. PDK Install Directory Structure assura_tsmc25rf_tech/ : Assura technology file directory calibre_tsmc25rf_tech/ : Calibre technology file directory readme : This file revision : Revision history assura_tech.lib : Assura tech file definition cds.lib : File containing the Cadence initialization file display.drf : Display resources file icc.rules : Icc auto P&R tech file models/ : Directory containing spice/spectre models skill/ : Directory containing callback and utilities skill code stream/ : Directory containing the stream in/out map file techfile : PDK technolog file tsmc25rf/ : TSMC PDK library 4. Supported Devices - BJT npn : NPN ***p : Vertical substrate PNP - FixedLayouts npn10 : NPN Fixed Layout, emitter size 10X10 npn2 : NPN Fixed Layout, emitter size 2X2 npn5 : NPN Fixed Layout, emitter size 5X5 ***p10 : Vertical substrate PNP Fixed Layout, emitter size 10X10 ***p2 : Vertical substrate PNP Fixed Layout, emitter size 2X2 ***p5 : Vertical substrate PNP Fixed Layout, emitter size 5X5 vsia : IP Tag Fixed Layout - logicDiodes dioden : N+/PW 1.2V diode diodenw : Nwell/PSUB diode diodep : P+/NW 1.2V diode - MOS nmos2v : 2.5 volt nominal VT NMOS transistor nmos2vdnw : 2.5 volt nominal VT NMOS transistor with deep nwell nmos3v : 3.3 volt nominal VT NMOS transistor nmos3vdnw : 3.3 volt nominal VT NMOS transistor with deep nwell nmosesd3v : 3.3 volt ESD NMOS transistor nmosmvt2v : 2.5 volt medium Vt NMOS transistor nmosnvt2v : 2.5 volt native NMOS transistor nmosnvt3v : 3.3V native VT NMOS transistor nmoszvt2v : 2.5 volt zero VT NMOS transistor pmos2v : 2.5 volt nominal VT PMOS transistor pmos3v : 3.3V nominal VT PMOS transistor pmosmvt2v : 2.5 volt medium Vt PMOS transistor pmoszvt2v : 2.5 volt zero VT PMOS transistor rfnmos2v10w : 2.5 volt RF NMOS transistor with w=10um rfnmos2v5w : 2.5 volt RF NMOS transistor with w=5um rfnmos3v10w : 3.3 volt RF NMOS transistor with w=10um rfnmos3v5w : 3.3 volt RF NMOS transistor with w=5um rfpmos2v10w : 2.5 volt RF PMOS transistor with w=10um rfpmos2v5w : 2.5 volt RF PMOS transistor with w=5um rfpmos3v10w : 3.3 volt RF PMOS transistor with w=10um rfpmos3v5w : 3.3 volt RF PMOS transistor with w=5um rftwnmos2v10w : 2.5 volt RF NMOS triple well transistor with w=10um - Parasitic pcapacitor : Cadence Analog Library Device presistor : Cadence Analog Library Device - Capacitor mimcap4 : M4 to CTM4 cap (metal to metal cap) nmoscap : nmos2v cap pmoscap : pmos2v cap - Diode dioden : N+/PW 1.2V diode diodenw : Nwell/PSUB diode diodep : P+/NW 1.2V diode - Inductor ind : Two-terminal Spiral Inductor. Fixed model sizes (2.5, 3.5, 4.5, 5.5, 6.5, 7.5 turns) - Resistor rm1 : Metal 1 resistor rm2 : Metal 2 resistor rm3 : Metal 3 resistor rm4 : Metal 4 resistor rm5 : Metal 5 resistor rnhpoly : N+ poly resistor without salicide rnlplus : N+ diffusion resistor with salicide rnlpoly : N+ poly resistor with salicide rnplus : N+ diffused resistor w/o salicide rnwell : NWell resistor under STI rnwod : NWell resistor under OD rphpoly : P+ poly resistor without salicide rphpoly_rf : P+ Poly resistor w/salicide, with RF model rplplus : P+ diffusion resistor with salicide rplpoly : P+ poly resistor without salicide rplpoly_rf : P+ Poly resistor w/salicide, with RF model rpplus : P+ Poly resistor w/o salicide, with RF model - Varactor jv : Junction varactor(Fixed model sizes (w=40um and l=0.42um fixed; fingers varies from 5 to 15)) varcap : nmos Varactor (Fixed width, length, and groups; variable fingers (2 to 8)) 5. CDF parameters - BJT "Emitter Size" "Multiplier" "Device initially off" "Estimated operating region" - FixedLayouts - logicDiodes "Multiplier" "Length (M)" "Width (M)" - MOS "l (M)" "w (M)" "Number of Fingers" "Connect Gates" "Gate Connection Side" "Source Area % Fill" "Source Cnt Position" "Drain Area % Fill" "Drain Cnt Position" "Include Left Contacts" "Include Right Contacts" "multiplier" "Body Tie % Fill" "Body Tie Position" "Calc Diff Params" "Source diffusion area" "Drain diffusion area" "Source diffusion periphery" "Drain diffusion periphery" - Parasitic "Capacitance" "Initial condition" "Model name" "Width" "Length" "Multiplier" "Scale factor" "Temp rise from ambient" "Temperature coefficient 1" "Temperature coefficient 2" "Temperature difference" "Number of Polynomial Coeffs" "Poly Coeff 1" "Poly Coeff 2" "Poly Coeff 3" "Poly Coeff 4" "Poly Coeff 5" "Poly Coeff 6" "Poly Coeff 7" "Poly Coeff 8" "Poly Coeff 9" "Poly Coeff 10" "Poly Coeff 11" "Poly Coeff 12" "Poly Coeff 13" "Poly Coeff 14" "Poly Coeff 15" "Poly Coeff 16" "Poly Coeff 17" "Poly Coeff 18" "Poly Coeff 19" "Resistance" "Resistance Form" "Generate noise?" "AC resistance" "Capacitance connected" - logicMOS "l (M)" "w (M)" "Number of Fingers" "Connect Gates" "Gate Connection Side" "Source Area % Fill" "Source Cnt Position" "Drain Area % Fill" "Drain Cnt Position" "Include Left Contacts" "Include Right Contacts" "multiplier" "Body Tie % Fill" "Body Tie Position" "Calc Diff Params" "Source diffusion area" "Drain diffusion area" "Source diffusion periphery" "Drain diffusion periphery" - Capacitor "Capacitance" "Spec" "l (M)" "w (M)" "Multiplier" "Default Bottom Pin Extention ?" "Number of Fingers" "Calc Diff Params" "Source diffusion area" "Drain diffusion area" "Source diffusion periphery" "Drain diffusion periphery" "Source lg" "Source ls" "Drain lg" "Drain ls" - Diode "Multiplier" "Length (M)" "Width (M)" - Inductor "Inner Radius" - Resistor "Resistance" "w (M)" "l (M)" "Entry Mode" "Number of Series Segments" "Number of Parallel Segments" "Segment Spacing (layout units)" "Multiplier" - Varactor "Number of Fingers" - logicBJT "Emitter Size" "Multiplier" "Device initially off" "Estimated operating region" - logicCap "Capacitance" "Spec" "l (M)" "w (M)" "Multiplier" "Number of Fingers" "Calc Diff Params" "Source diffusion area" "Drain diffusion area" "Source diffusion periphery" "Drain diffusion periphery" "Source lg" "Source ls" "Drain lg" "Drain ls" - logicFixedLayouts - logicRes "Resistance" "w (M)" "l (M)" "Entry Mode" "Number of Series Segments" "Number of Parallel Segments" "Segment Spacing (layout units)" "Multiplier" - MOS "l (M)" "w (M)" "Number of Fingers" "Connect Gates" "Gate Connection Side" "Source Area % Fill" "Source Cnt Position" "Drain Area % Fill" "Drain Cnt Position" "Include Left Contacts" "Include Right Contacts" "multiplier" "Body Tie % Fill" "Body Tie Position" "Calc Diff Params" "Source diffusion area" "Drain diffusion area" "Source diffusion periphery" "Drain diffusion periphery" - BJT "Emitter Size" "Multiplier" "Device initially off" "Estimated operating region" - Resistor "Resistance" "w (M)" "l (M)" "Entry Mode" "Number of Series Segments" "Number of Parallel Segments" "Segment Spacing (layout units)" "Multiplier" - Diode "Multiplier" "Length (M)" "Width (M)" - FixedLayouts - Capacitor "Capacitance" "Spec" "l (M)" "w (M)" "Multiplier" "Default Bottom Pin Extention ?" "Number of Fingers" "Calc Diff Params" "Source diffusion area" "Drain diffusion area" "Source diffusion periphery" "Drain diffusion periphery" "Source lg" "Source ls" "Drain lg" "Drain ls" 6. Views Provided - BJT Terminals (C B E) symbol, spectre, hspiceS, auLVS, auCDL, ivpcell, layout - FixedLayouts Terminals symbol, spectre, hspiceS, auLVS, auCDL, ivpcell, layout - logicDiodes Terminals (PLUS MINUS) symbol, spectre, hspiceS, auLVS, auCDL, ivpcell, layout - MOS Terminals (D G S B) (D G S S) (D G S) symbol, spectre, hspiceS, auLVS, auCDL, ivpcell, layout - Parasitic Terminals (PLUS MINUS) symbol, spectre, hspiceS, auLVS, auCDL, ivpcell, layout - logicMOS Terminals (D G S B) symbol, spectre, hspiceS, auLVS, auCDL, ivpcell, layout - Capacitor Terminals (TOP BOT) (D G S B) symbol, spectre, hspiceS, auLVS, auCDL, ivpcell, layout - Diode Terminals (PLUS MINUS) symbol, spectre, hspiceS, auLVS, auCDL, ivpcell, layout - Inductor Terminals (PLUS MINUS) symbol, spectre, hspiceS, auLVS, auCDL, ivpcell, layout - LOGIC_DEVICES Terminals symbol, spectre, hspiceS, auLVS, auCDL, ivpcell, layout - Resistor Terminals (PLUS MINUS) (PLUS MINUS B) nil symbol, spectre, hspiceS, auLVS, auCDL, ivpcell, layout - Varactor Terminals (PLUS MINUS) symbol, spectre, hspiceS, auLVS, auCDL, ivpcell, layout - logicBJT Terminals (C B E) symbol, spectre, hspiceS, auLVS, auCDL, ivpcell, layout - logicCap Terminals (D G S B) symbol, spectre, hspiceS, auLVS, auCDL, ivpcell, layout - logicFixedLayouts Terminals symbol, spectre, hspiceS, auLVS, auCDL, ivpcell, layout - logicRes Terminals (PLUS MINUS) (PLUS MINUS B) nil symbol, spectre, hspiceS, auLVS, auCDL, ivpcell, layout - MOS Terminals (D G S B) (D G S S) (D G S) symbol, spectre, hspiceS, auLVS, auCDL, ivpcell, layout - BJT Terminals (C B E) symbol, spectre, hspiceS, auLVS, auCDL, ivpcell, layout - Resistor Terminals (PLUS MINUS) (PLUS MINUS B) nil symbol, spectre, hspiceS, auLVS, auCDL, ivpcell, layout - Diode Terminals (PLUS MINUS) symbol, spectre, hspiceS, auLVS, auCDL, ivpcell, layout - FixedLayouts Terminals symbol, spectre, hspiceS, auLVS, auCDL, ivpcell, layout - Capacitor Terminals (TOP BOT) (D G S B) symbol, spectre, hspiceS, auLVS, auCDL, ivpcell, layout 7. Device Specifications Device Terminals Spectre Hspice auCdl auLvs Model Model Model Model BJT npn (C B E) npn10 npn10 NV npn npn (C B E) npn10 npn10 NV npn ***p (C B E) pnp10 pnp10 PV ***p ***p (C B E) pnp10 pnp10 PV ***p BJT npn (C B E) npn10 npn10 NV npn npn (C B E) npn10 npn10 NV npn ***p (C B E) pnp10 pnp10 PV ***p ***p (C B E) pnp10 pnp10 PV ***p Capacitor mimcap4 (TOP BOT) mimcap mimcap mimcap mimcap4 mimcap4 (TOP BOT) mimcap mimcap mimcap mimcap4 nmoscap (D G S B) nch nch N nmos2v nmoscap (D G S B) nch nch N nmos2v pmoscap (D G S B) pch pch P pmos2v pmoscap (D G S B) pch pch P pmos2v Capacitor mimcap4 (TOP BOT) mimcap mimcap mimcap mimcap4 mimcap4 (TOP BOT) mimcap mimcap mimcap mimcap4 nmoscap (D G S B) nch nch N nmos2v nmoscap (D G S B) nch nch N nmos2v pmoscap (D G S B) pch pch P pmos2v pmoscap (D G S B) pch pch P pmos2v Diode dioden (PLUS MINUS) ndio ndio DN dioden dioden (PLUS MINUS) ndio ndio DN dioden diodenw (PLUS MINUS) nwdio nwdio DW diodenw diodenw (PLUS MINUS) nwdio nwdio DW diodenw diodep (PLUS MINUS) pdio pdio DP diodep diodep (PLUS MINUS) pdio pdio DP diodep Diode dioden (PLUS MINUS) ndio ndio DN dioden dioden (PLUS MINUS) ndio ndio DN dioden diodenw (PLUS MINUS) nwdio nwdio DW diodenw diodenw (PLUS MINUS) nwdio nwdio DW diodenw ... ...

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