ldpc-encode
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：3482KB
下载次数：85
上传日期：2012-10-20 22:19:50
上 传 者：
19891002dongdong
说明： 深空通信中AR4JA码编码的研究与实现，ＡＲ４ＪＡ码是ＬＤＰＣ码的一种，文件中是Ｖｅｒｉｌｏｇ语言的硬件实现。
(Research and Implementation of the Deep Space Communications AR4JA coding, AR4JA code LDPC codes a hardware implementation of the Verilog language file.)
文件列表:
encode\ldpc\counter_pin.lfp (10505, 2011-04-28)
encode\ldpc\counter_pin.ucf (7957, 2011-04-28)
encode\ldpc\device_usage_statistics.html (36798, 2011-04-28)
encode\ldpc\fuse.log (1832, 2011-05-04)
encode\ldpc\gen.asy (335, 2010-12-20)
encode\ldpc\gen.coe (1109, 2010-12-20)
encode\ldpc\gen.mif (1040, 2010-12-20)
encode\ldpc\gen.ngc (21315, 2010-12-20)
encode\ldpc\gen.sym (565, 2010-12-20)
encode\ldpc\gen.v (3953, 2010-12-20)
encode\ldpc\gen.veo (2985, 2010-12-20)
encode\ldpc\gen.vhd (4345, 2010-12-20)
encode\ldpc\gen.vho (3389, 2010-12-20)
encode\ldpc\gen.xco (1811, 2010-12-20)
encode\ldpc\gen_flist.txt (142, 2010-12-20)
encode\ldpc\gen_xmdf.tcl (3096, 2010-12-20)
encode\ldpc\isim\isim.tmp_save\_1 (13527, 2011-05-30)
encode\ldpc\isim\isimcrash.log (0, 2011-05-30)
encode\ldpc\isim\simulate_dofile.log (15, 2011-05-30)
encode\ldpc\isim\simulate_dofile.log_back (41, 2010-12-20)
encode\ldpc\isim\work\gen.sdb (2560, 2010-12-20)
encode\ldpc\isim\work\gen.vdb (4722, 2011-05-04)
encode\ldpc\isim\work\glbl.sdb (3685, 2010-12-20)
encode\ldpc\isim\work\ldpc_code.sdb (7718, 2010-12-20)
encode\ldpc\isim\work\t2.sdb (2720, 2010-12-20)
encode\ldpc\isim\work\t3.sdb (2776, 2010-12-20)
encode\ldpc\isim\work\t4.sdb (3636, 2010-12-20)
encode\ldpc\isim\work\test.sdb (2890, 2010-12-20)
encode\ldpc\isim\_tmp\work\m_00000000000042853097_3427758315.c (21430, 2010-12-20)
encode\ldpc\isim\_tmp\work\m_00000000000042853097_3427758315.didat (3900, 2010-12-20)
encode\ldpc\isim\_tmp\work\m_00000000000042853097_3427758315.nt.obj (6886, 2010-12-20)
encode\ldpc\isim\_tmp\work\m_00000000000310165858_3427758315.c (19863, 2010-12-20)
encode\ldpc\isim\_tmp\work\m_00000000000310165858_3427758315.didat (3900, 2010-12-20)
encode\ldpc\isim\_tmp\work\m_00000000000310165858_3427758315.nt.obj (6742, 2010-12-20)
encode\ldpc\isim\_tmp\work\m_00000000000515014449_1985558087.c (4078, 2010-12-20)
encode\ldpc\isim\_tmp\work\m_00000000000515014449_1985558087.didat (3444, 2010-12-20)
encode\ldpc\isim\_tmp\work\m_00000000000515014449_1985558087.nt.obj (2788, 2010-12-20)
encode\ldpc\isim\_tmp\work\m_00000000000866782574_2073120511.c (7183, 2011-05-04)
encode\ldpc\isim\_tmp\work\m_00000000000866782574_2073120511.didat (4836, 2011-05-04)
... ...
The following files were generated for 'gen' in directory
D:\ISE\ldpc:
gen.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
gen.mif:
Memory Initialization File which is automatically generated by the
CORE Generator System for some modules when a simulation flow is
specified. A MIF data file is used to support HDL functional
simulation of modules which use arrays of values.
gen.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
gen.sym:
Please see the core data sheet.
gen.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
gen.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
gen.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
gen.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
gen.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
gen_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
gen_readme.txt:
Text file indicating the files generated and how they are used.
gen_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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