modelsim-sdram-sim
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：182KB
下载次数：24
上传日期：2012-11-02 19:14:27
上 传 者：
icebin
说明： 包括sdram 测试平台，sdram控制器，sdram行为模型。
(Includes sdram testbench, sdram controller, sdram behavior model.
)
文件列表:
part2_16\model\mt48lc8m16a2.v (43909, 2006-10-15)
part2_16\rtl\Command.v (17532, 2005-06-18)
part2_16\rtl\control_interface.v (8494, 2004-11-28)
part2_16\rtl\Params.v (935, 2006-10-15)
part2_16\rtl\sdr_data_path.v (2760, 2004-08-02)
part2_16\rtl\sdr_sdram.v (7237, 2006-10-15)
part2_16\sim\Command.v (17532, 2005-06-18)
part2_16\sim\control_interface.v (8494, 2004-11-28)
part2_16\sim\mt48lc8m16a2.v (43909, 2006-10-15)
part2_16\sim\mt48lc8m16a2.v.bak (43870, 2006-10-15)
part2_16\sim\Params.v (935, 2006-10-15)
part2_16\sim\Params.v.bak (935, 2006-10-15)
part2_16\sim\sdram_test_tb.v (7942, 2006-10-15)
part2_16\sim\sdram_test_tb.v.bak (7874, 2006-10-15)
part2_16\sim\sdr_data_path.v (2760, 2004-08-02)
part2_16\sim\sdr_sdram.v (7237, 2006-10-15)
part2_16\sim\sdr_sdram.v.bak (7233, 2005-06-14)
part2_16\sim\sdtest.cr.mti (2161, 2006-11-02)
part2_16\sim\sdtest.mpf (23148, 2006-11-01)
part2_16\sim\vish_stacktrace.vstf (14003, 2006-10-15)
part2_16\sim\vsim.wlf (32768, 2006-11-01)
part2_16\sim\work\command\verilog.asm (37891, 2006-11-01)
part2_16\sim\work\command\_primary.dat (4825, 2006-11-01)
part2_16\sim\work\command\_primary.vhd (1319, 2006-11-01)
part2_16\sim\work\control_interface\verilog.asm (22288, 2006-11-01)
part2_16\sim\work\control_interface\_primary.dat (2787, 2006-11-01)
part2_16\sim\work\control_interface\_primary.vhd (1105, 2006-11-01)
part2_16\sim\work\mt48lc8m16a2\verilog.asm (234945, 2006-11-01)
part2_16\sim\work\mt48lc8m16a2\_primary.dat (24815, 2006-11-01)
part2_16\sim\work\mt48lc8m16a2\_primary.vhd (1291, 2006-11-01)
part2_16\sim\work\sdram_test\verilog.asm (60601, 2006-10-15)
part2_16\sim\work\sdram_test\_primary.dat (6618, 2006-10-15)
part2_16\sim\work\sdram_test\_primary.vhd (1580, 2006-10-15)
part2_16\sim\work\sdram_test_tb\verilog.asm (59353, 2006-11-01)
part2_16\sim\work\sdram_test_tb\_primary.dat (6260, 2006-11-01)
part2_16\sim\work\sdram_test_tb\_primary.vhd (1441, 2006-11-01)
part2_16\sim\work\sdr_data_path\verilog.asm (5465, 2006-11-01)
part2_16\sim\work\sdr_data_path\_primary.dat (798, 2006-11-01)
part2_16\sim\work\sdr_data_path\_primary.vhd (502, 2006-11-01)
part2_16\sim\work\sdr_sdram\verilog.asm (19719, 2006-11-01)
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