DAC_Load
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：7KB
下载次数：9
上传日期：2012-11-19 06:43:34
上 传 者：
VladimirD70
说明： Load DAC by SPI protocol
-- Unit provides serial load of DAC trough SPI 3-wire serial interface
-- It sends 24-bit word, format of the word:
-- 4-bit command: C3-C0, 4x don t care bits, 12-bit data: d11-d0, 4x don t care bits
--
-- Serial interface outputs:
-- SDI - Serial Interface Data sent to DAC
-- SCK - Serial Interface Clock
-- CSLD - Serial Interface Chip Select/Load
--
-- DAC word length = 24 bit:
-- --------------------------
-- MSB
-- 4 bits - DAC command
-- 4 bits - don t care values
-- 12 bits - "gain" word
-- 4 bits - don t care values
-- LSB
-- --------------------------
--
-- Dependencies:
--
-- This unit needs the following files:
-- 1) counter.vhd
-- 2) SEQUENCE.vhd
-- 3) rising.vhd
-- 4) falling.vhd
-- 5) Dline1.vhd
-- 4) useful.vhd
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
文件列表:
counter.vhd (1897, 2008-06-13)
DacLoad.vhd (10458, 2008-12-04)
dline1.vhd (1791, 2008-01-16)
falling.vhd (579, 2008-12-02)
rising.vhd (1218, 2008-06-12)
SEQUENCE.vhd (2346, 2008-12-02)
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