bist_rev_1_5

所属分类:串口编程
开发工具:Visual C++
文件大小:1699KB
下载次数:20
上传日期:2006-07-24 16:21:44
上 传 者shinyon
说明:  Viertex 2 开发板的接口程序,使用VC编写。
(100 2 development board interface, the use of VC prepared.)

文件列表:
bist_rev_1_5 (0, 2006-07-08)
bist_rev_1_5\system.mhs (13855, 2005-06-17)
bist_rev_1_5\system.mss (2376, 2005-03-25)
bist_rev_1_5\system.xmp (1887, 2005-06-20)
bist_rev_1_5\pcores (0, 2006-07-08)
bist_rev_1_5\pcores\plb_at_v1_01_b (0, 2006-07-08)
bist_rev_1_5\pcores\plb_at_v1_01_b\netlist (0, 2006-07-08)
bist_rev_1_5\pcores\plb_at_v1_01_b\netlist\coregen_fifo.edn (62184, 2005-02-17)
bist_rev_1_5\pcores\plb_at_v1_01_b\netlist\plb_at.ngc (2556985, 2005-05-04)
bist_rev_1_5\pcores\plb_at_v1_01_b\devl (0, 2006-07-08)
bist_rev_1_5\pcores\plb_at_v1_01_b\devl\at_xst.prj (5426, 2005-05-04)
bist_rev_1_5\pcores\plb_at_v1_01_b\devl\at_xst.scr (164, 2005-05-04)
bist_rev_1_5\pcores\plb_at_v1_01_b\data (0, 2006-07-08)
bist_rev_1_5\pcores\plb_at_v1_01_b\data\plb_at_v2_1_0.bbd (412, 2005-05-04)
bist_rev_1_5\pcores\plb_at_v1_01_b\data\plb_at_v2_1_0.mpd (3149, 2005-05-04)
bist_rev_1_5\pcores\plb_at_v1_01_b\data\plb_at_v2_1_0.pao (0, 2005-06-17)
bist_rev_1_5\pcores\or_gate_v1_00_a (0, 2006-07-08)
bist_rev_1_5\pcores\or_gate_v1_00_a\hdl (0, 2006-07-08)
bist_rev_1_5\pcores\or_gate_v1_00_a\hdl\vhdl (0, 2006-07-08)
bist_rev_1_5\pcores\or_gate_v1_00_a\hdl\vhdl\or_gate.vhd (303, 2005-02-17)
bist_rev_1_5\pcores\or_gate_v1_00_a\data (0, 2006-07-08)
bist_rev_1_5\pcores\or_gate_v1_00_a\data\or_gate_v2_1_0.mpd (205, 2005-02-17)
bist_rev_1_5\pcores\or_gate_v1_00_a\data\or_gate_v2_1_0.pao (29, 2005-02-17)
bist_rev_1_5\pcores\opb_ac97_v2_00_a (0, 2006-07-08)
bist_rev_1_5\pcores\opb_ac97_v2_00_a\hdl (0, 2006-07-08)
bist_rev_1_5\pcores\opb_ac97_v2_00_a\hdl\vhdl (0, 2006-07-08)
bist_rev_1_5\pcores\opb_ac97_v2_00_a\hdl\vhdl\ac97.do (3050, 2005-02-18)
bist_rev_1_5\pcores\opb_ac97_v2_00_a\hdl\vhdl\ac97.mpf (24065, 2005-02-18)
bist_rev_1_5\pcores\opb_ac97_v2_00_a\hdl\vhdl\ac97_command_rom.vhd (3893, 2005-02-18)
bist_rev_1_5\pcores\opb_ac97_v2_00_a\hdl\vhdl\ac97_core.do (1594, 2005-02-18)
bist_rev_1_5\pcores\opb_ac97_v2_00_a\hdl\vhdl\ac97_core.vhd (24894, 2005-02-18)
bist_rev_1_5\pcores\opb_ac97_v2_00_a\hdl\vhdl\ac97_fifo.do (1227, 2005-02-18)
bist_rev_1_5\pcores\opb_ac97_v2_00_a\hdl\vhdl\ac97_fifo.vhd (29087, 2005-02-18)
bist_rev_1_5\pcores\opb_ac97_v2_00_a\hdl\vhdl\ac97_if.do (288, 2005-02-18)
bist_rev_1_5\pcores\opb_ac97_v2_00_a\hdl\vhdl\ac97_if.vhd (11332, 2005-02-18)
bist_rev_1_5\pcores\opb_ac97_v2_00_a\hdl\vhdl\ac97_if_pkg.vhd (2156, 2005-02-18)
bist_rev_1_5\pcores\opb_ac97_v2_00_a\hdl\vhdl\ac97_model.vhd (14137, 2005-02-18)
bist_rev_1_5\pcores\opb_ac97_v2_00_a\hdl\vhdl\ac97_timing.do (151, 2005-02-18)
bist_rev_1_5\pcores\opb_ac97_v2_00_a\hdl\vhdl\ac97_timing.vhd (6089, 2005-02-18)
bist_rev_1_5\pcores\opb_ac97_v2_00_a\hdl\vhdl\bram_fifo.vhd (6641, 2005-02-18)
... ...

Files: ac97_timing.vhd Generates timing signals for AC97 core ac97_core.vhd Core AC97 controller interface (no buffering) srl_fifo.vhd Parameterizable FIFO module ac97_fifo.vhd AC97 interface with a data fifo opb_ac97.vhd OPB interface to core ac97_model.vhd Simplistic behavioral model of AC97 protocol TESTBENCH_ac97_package.vhd Common simulation procedures TESTBENCH_ac97_core.vhd Testbench for ac97_core TESTBENCH_ac97_fifo.vhd Testbench for ac97_fifo

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