FPGA--SDRAM

所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:19461KB
下载次数:3
上传日期:2012-11-22 11:16:11
上 传 者官阿发
说明:  SDRAM:Synchronous Dynamic Random Access Memory
( 同步动态随机存储器,同步是指 Memory工作需要同步时钟,内部的命令的发送与数据的传输都以它为基准;动态是指存储阵列需要不断的刷新来保证数据不丢失;随机是指数据不是线性依次存储,而是自由指定地址进行数据读写。 )

文件列表:
FPGA读写SDRAM的实例\使用说明请参看右侧注释====〉〉.txt (774, 2008-01-28)
FPGA读写SDRAM的实例\vga_system\altpll0.bsf (3937, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\altpll0.ppf (497, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\altpll0.v (17134, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\altpll0_bb.v (13096, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\altpll0_wave0.jpg (83995, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\altpll0_waveforms.html (620, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\burst_0.v (14922, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\cpu.v (431965, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\cpu_bht_ram.mif (2392, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\cpu_dc_tag_ram.mif (920, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\cpu_ic_tag_ram.mif (1881, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\cpu_jtag_debug_module.v (12429, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\cpu_jtag_debug_module_wrapper.v (9850, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\cpu_mult_cell.v (6103, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\cpu_ociram_default_contents.mif (5878, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\cpu_rf_ram_a.mif (600, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\cpu_rf_ram_b.mif (600, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\cpu_test_bench.v (39223, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\FreeDevDAV.tcl (13123, 2006-09-04)
FPGA读写SDRAM的实例\vga_system\freedev_vga_inst.v (4556, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\jtag_uart.v (22495, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\led_pio.v (1898, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\sdram.v (23342, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\sdram_test_component.v (9274, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\sopc_add_qip_file.tcl (146, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\sopc_builder_log.txt (3087, 2007-11-10)
FPGA读写SDRAM的实例\vga_system\sysid.v (1335, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\sys_clk_timer.v (6898, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\vga_fifo.v (8007, 2007-09-20)
FPGA读写SDRAM的实例\vga_system\vga_sys.bsf (8084, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\vga_sys.ptf (100403, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\vga_sys.ptf.bak (88476, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\vga_sys.ptf.pre_generation_ptf (60004, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\vga_sys.qip (271, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\vga_sys.sopc (23437, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\vga_sys.v (456278, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\vga_system.asm.rpt (7871, 2008-03-01)
FPGA读写SDRAM的实例\vga_system\vga_system.bdf (31459, 2007-11-09)
FPGA读写SDRAM的实例\vga_system\vga_system.done (26, 2008-03-01)
... ...

Readme - Hello World Software Example DESCRIPTION: Simple program that prints "Hello from Nios II" REQUIREMENTS: This example will run on the following Nios II designs, targeting the Nios Stratix & Cyclone development boards: - Standard - Full Featured - Fast - Low Cost The memory footprint of this hosted application is ~69 kbytes by default using the standard reference deisgn. For a reduced footprint version of this template, and an explanation of how to reduce the memory footprint for a given application, see the "small_hello_world" template. PERIPHERALS USED: This example exercises the following peripherals: - STDOUT device (UART or JTAG UART) SOFTWARE SOURCE FILES: This example includes the following software source files: - hello_world.c: Everyone needs a Hello World program, right? BOARD/HOST REQUIREMENTS: This example requires only a JTAG connection with a Nios Development board. If the host communication settings are changed from JTAG UART (default) to use a conventional UART, a serial cable between board DB-9 connector and the host is required.

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